Search results

Create the page "Data processing" on this wiki! See also the search results found.

• MH10 core memory
  ...least one per CPU); the others are used by [[channel]]s (such as a [[DF10 Data Channel|DF10]]) for [[mass storage]] such as [[disk]]s.
  3 KB (407 words) - 12:40, 5 November 2023
• MF20 MOS memory
  ...ovided to protect the memory contents; an MF20 44-[[bit]] word contains 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MF20 can be
  2 KB (278 words) - 15:50, 24 October 2022
• MG20 MOS memory
  <!-- The [[access time]] is .80 µseconds at the [[Central Processing Unit|CPU]], and the [[cycle time]] is 1.00 µseconds (both for the first [[ ...G20 almost certainly shared the MF20's 44-[[bit]] word, which contained 36 data bits, 6 ECC bits, 1 bit of ECC [[parity]], and 1 spare bit. The MG20 could
  2 KB (355 words) - 15:49, 24 October 2022
• RH20 MASSBUS controller
  ...ory of the system, to allow it to use [[Direct Memory Access|DMA]] to move data directly from devices to main memory, without needing CPU intervention.
  2 KB (294 words) - 12:59, 12 November 2023
• DLV11-F asynchronous serial line interface
  ...ters for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when a '[[asynchronous serial line|break]]' is seen; it can also
  3 KB (469 words) - 01:19, 17 February 2023
• KE11-A Extended Arithmetic Element
  ...hift operations. As a UNIBUS peripheral, not integrated into the [[Central Processing Unit|CPU]], it was also usable with other models, e.g. the [[PDP-11/05]] an ...20-777336. The operation to be performed is selected by the register which data is written to. Registers which hold results are readable, but many of the o
  5 KB (680 words) - 21:17, 2 July 2023
• Able UNIVERTER
  ...y the low-level details differ. (E.g. the UNIBUS carries [[address]]es and data on separate [[conductor|lines]], whereas the QBUS carries them both on a se ...s that the [[bus grant|bus arbiter]], and the interrupt-fielding [[Central Processing Unit|processor]], be on the QBUS. The UNIVERTER does not have to be at the
  2 KB (251 words) - 18:32, 5 December 2022
• Bus Arbitration on the Unibus and QBUS
  ...(sometimes multiple processors) and peripheral devices together and allows data transfers between the various components. As a general rule, one and only o ...asserts BBSY and becomes the bus master. The requesting device now can run data transfer bus cycles. When it's done, the requesting device negates SACK and
  21 KB (3,685 words) - 04:35, 28 November 2023
• DM11-BB Modem Control Option
  ...be connected to [[modem]]s. It could be set to [[interrupt]] the [[Central Processing Unit|CPU]] when a modem control line (Ring, Carrier, etc) changed state. *DTR - Data Terminal Ready; allow modem to enter data mode
  7 KB (975 words) - 04:15, 18 February 2023
• KA650 CPU
  {{InfoboxVAXCPU-Data The '''KA650''' is the [[Central Processing Unit|CPU]] used in several [[Digital Equipment Corporation|DEC]] [[MicroVAX
  3 KB (369 words) - 08:32, 12 September 2023
• KA650 Main Memory System
  ...[[KA650 CPU]], and later [[KA655 CPU]]. It is split between the [[Central Processing Unit|CPU]] card, which contains the main memory controller, and a number of ...XA21), which are used as bank selection when using 256kxX DRAM chips. The data lines are carried to the RAM cards through a 50 conductor [[flat cable|ribb
  42 KB (5,493 words) - 15:53, 23 May 2024
• Three cycle data break
  ...ss storage]]) to [[main memory]], used on a number of [[List of Programmed Data Processors|early DEC computers]]. ...update the transfer address, and finally store or retrieve the actual I/O data word.
  1 KB (235 words) - 22:06, 15 June 2022
• DZV11 asynchronous serial line interface
  ...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line. |Transmit Data Register || TDR || 760106
  5 KB (684 words) - 11:36, 17 February 2023
• DZQ11 asynchronous serial line interface
  ...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line. |Transmit Data Register || TDR || 760106
  5 KB (677 words) - 11:45, 17 February 2023
• Tandberg TDV 1200
  | manufacturer = Tandberg Data ...' [[video terminal]] was produced by [[Tandberg Data]] and sold by [[Norsk Data]] (ND) as product number 110140. It was also known as ND Display Terminal 1
  3 KB (421 words) - 22:10, 9 May 2021
• Bank switching
  Rather, it is most commonly found in machines whose [[Central Processing Unit|CPU]] [[architecture]] provides a limited [[address space]] - less tha ...ferent bank. (In some systems, instructions are fetched from one bank, and data from a potentially different bank.)
  3 KB (468 words) - 15:36, 7 November 2021
• PDP-8 Memory Extension units
  ...fetch]]es. (The DF is only used for ''indirect'' data word fetches; direct data fetches - i.e. in the same page as the instruction - use the IF.) They coul ...occurs; and the Break Field Register, a 3 bit wide register used during [[data break]] [[Direct Memory Access|DMA]] operations, to select the field those
  4 KB (614 words) - 21:02, 7 August 2022
• Pure code
  ...iety of reasons (including not interacting well with a number of [[Central Processing Unit|CPU]] optimizations), so essentially all object code is now pure code. ...the [[instruction]]s to be segregated (in the [[address space]]) from the data, since the latter would presumably differ among the instances of the progra
  956 bytes (155 words) - 14:46, 12 June 2021
• DA10 Twelve- and Eighteen-Bit Computer Interface
  ...20 In/Out Bus Controller]] to provide an I/O bus. Unlike the [[DL10 PDP-11 Data Link|DL10]], it didn't use [[Direct Memory Access|DMA]], just [[programmed The DA10 is used in the DC68A Data Communication System, which uses a [[PDP-8/I]].
  3 KB (442 words) - 14:51, 7 March 2023
• Shift register
  ...rpose of the shift register. For instance, a shift register in a [[Central Processing Unit|CPU]], used for arithmetic purposes, would typically be both loaded an Another common use of a shift register is to take data being sent between two subsystems in serial form, using a single [[conducto
  1 KB (236 words) - 20:43, 4 August 2021

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)