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• KA650 Main Memory System
  ...[[KA650 CPU]], and later [[KA655 CPU]]. It is split between the [[Central Processing Unit|CPU]] card, which contains the main memory controller, and a number of ...XA21), which are used as bank selection when using 256kxX DRAM chips. The data lines are carried to the RAM cards through a 50 conductor [[flat cable|ribb
  42 KB (5,493 words) - 15:53, 23 May 2024
• Three cycle data break
  ...ss storage]]) to [[main memory]], used on a number of [[List of Programmed Data Processors|early DEC computers]]. ...update the transfer address, and finally store or retrieve the actual I/O data word.
  1 KB (235 words) - 22:06, 15 June 2022
• DZV11 asynchronous serial line interface
  ...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line. |Transmit Data Register || TDR || 760106
  5 KB (684 words) - 11:36, 17 February 2023
• DZQ11 asynchronous serial line interface
  ...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line. |Transmit Data Register || TDR || 760106
  5 KB (677 words) - 11:45, 17 February 2023
• Tandberg TDV 1200
  | manufacturer = Tandberg Data ...' [[video terminal]] was produced by [[Tandberg Data]] and sold by [[Norsk Data]] (ND) as product number 110140. It was also known as ND Display Terminal 1
  3 KB (421 words) - 22:10, 9 May 2021
• Bank switching
  Rather, it is most commonly found in machines whose [[Central Processing Unit|CPU]] [[architecture]] provides a limited [[address space]] - less tha ...ferent bank. (In some systems, instructions are fetched from one bank, and data from a potentially different bank.)
  3 KB (468 words) - 15:36, 7 November 2021
• PDP-8 Memory Extension units
  ...fetch]]es. (The DF is only used for ''indirect'' data word fetches; direct data fetches - i.e. in the same page as the instruction - use the IF.) They coul ...occurs; and the Break Field Register, a 3 bit wide register used during [[data break]] [[Direct Memory Access|DMA]] operations, to select the field those
  4 KB (614 words) - 21:02, 7 August 2022
• Pure code
  ...iety of reasons (including not interacting well with a number of [[Central Processing Unit|CPU]] optimizations), so essentially all object code is now pure code. ...the [[instruction]]s to be segregated (in the [[address space]]) from the data, since the latter would presumably differ among the instances of the progra
  956 bytes (155 words) - 14:46, 12 June 2021
• DA10 Twelve- and Eighteen-Bit Computer Interface
  ...20 In/Out Bus Controller]] to provide an I/O bus. Unlike the [[DL10 PDP-11 Data Link|DL10]], it didn't use [[Direct Memory Access|DMA]], just [[programmed The DA10 is used in the DC68A Data Communication System, which uses a [[PDP-8/I]].
  3 KB (442 words) - 14:51, 7 March 2023
• Shift register
  ...rpose of the shift register. For instance, a shift register in a [[Central Processing Unit|CPU]], used for arithmetic purposes, would typically be both loaded an Another common use of a shift register is to take data being sent between two subsystems in serial form, using a single [[conducto
  1 KB (236 words) - 20:43, 4 August 2021
• Serial
  ...essing where one [[bit]] is handled at a time, with successive bits in any data item (such as a [[word]]) being handled in later time slots. ...and the [[arithmetic logic unit|ALU]] in a [[serial computer]]'s [[Central Processing Unit|CPU]], which would have only a single-bit adder, and to add two number
  688 bytes (116 words) - 23:28, 6 August 2021
• DV11 Communications Multiplexer
  ...[[flat cable]]s connect the main unit to each distribution panel (two for data and [[clock]], two for modem control.). ...different 16-[[bit]] [[instruction]]s (BRANCH A, BRANCH B, ALU OP, RAM OP, DATA XFR, NPR OP, SET/CLR OP, BCC OP), and an [[arithmetic logic unit|ALU]] buil
  6 KB (823 words) - 04:24, 18 February 2023
• International Network Working Group
  ...was given a formal home in the [[International Federation for Information Processing]], as IFIP Working Group 6.1 - Computer Communication.
  1 KB (185 words) - 18:10, 20 January 2024
• UNIBUS Device Addresses
  [[Central Processing Unit|CPU]] [[register]]s marked as "[[PDP-11/73|11/73]]" also appear in the | 777732 || Diagnostic Controller Data (11/84)
  7 KB (927 words) - 11:26, 12 November 2021
• Alto-1822 Interface
  ...[[Central Processing Unit|CPU]] bus, and used custom [[microcode]] to move data to and from [[main memory]]. It was [[full-duplex]], but included no [[buff
  3 KB (443 words) - 14:59, 21 May 2023
• DMA Request and Grant
  ...there; they are for a [[peripheral|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. The [[Central Processing Unit|CPU]] may not perform ''any'' action (i.e. an [[interrupt]]) while the
  1 KB (190 words) - 04:01, 21 November 2021
• Datapoint 2200
  The base unit included a [[CPU|Central Processing Unit]], a small amount of [[main memory]], two digital cassette [[magnetic ...have an 8-bit [[operation code]], and an optional single byte of immediate data, or two bytes of [[address]].
  5 KB (814 words) - 20:05, 4 June 2023
• DW780 Unibus Adapter
  * M8272 - UBA Map and Data Path (UMD) ...a custom 6-slot [[backplane]] (normally mounted next to the main [[Central Processing Unit|CPU]] backplane). 2 slots (on the back of the backplane) are used to h
  2 KB (314 words) - 21:03, 15 May 2024
• KA780 CPU
  The '''KA780 CPU''' was the [[Central Processing Unit|CPU]] for the [[VAX-11/780]]. | 13 || M8229 || DAP || Data Path
  2 KB (259 words) - 00:08, 3 January 2022
• MA780 Multiport Memory Option
  * in each connected [[Central Processing Unit|CPU]] (between 2 and 4), an '''MA780-C Port Interface''', held in anot | 11 || M8212 || MDT || Memory Data Paths
  3 KB (487 words) - 14:56, 15 May 2024

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