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• Talk:KL10
  ...ed, and the second to have extended addressing. The last one has a bigger cache. ...e/Paging Upgrade", which focusses on what it does, but it sounds like that cache was an upgrade to the PV. So I'm not sure the PW is fundamentally different
  17 KB (2,818 words) - 12:17, 3 April 2024
• PDP-11 family differences appendix
  ! Item !! 03 !! 23/24 !! 73/83/93 !! 04 !! 05 !! 20 !! 34 !! 40 !! 44 !! 45 !! 70 | Explicit [[cache|caching]] control per-[[segment]] || - || - || @ || - || - || - || || - ||
  2 KB (343 words) - 03:12, 13 September 2020
• UNIBUS Device Addresses
  | 772440-76 || TU16/45/77 | 777744 || Memory Error (11/70, /60, /44, /73) Cache Memory Error (11/34 w/ KK11-A)
  7 KB (927 words) - 11:26, 12 November 2021
• DEC Semiconductor Chips
  | RIGEL Backup Cache Chip [[#ref_27|[27]]] | Mistral Backup Cache Controller chip (C-chip) [[#ref_29|[29]]]
  36 KB (3,420 words) - 05:36, 5 November 2022
• Installing MicroVMS V4.6 on SIMH
  Beginning installation of PROG V4.6 at 15:45 Installation of PROG V4.6 completed at 15:45
  65 KB (7,949 words) - 21:58, 19 August 2023
• VAX 85xx, 87xx, and 88xx systems
  ...t design bugs early. ECL technology and a two-phase clock system achieve a 45-nanosecond cycle time. [[Microcode|Micro instructions]] are processed simul * C Box = Cache Box
  8 KB (1,158 words) - 03:12, 23 May 2024
• Installing ULTRIX-11 V1.0 on SIMH
  CPU 1 PDP11/23, 24, 34, 40, 44, 45, 55, 60, 70 < 23 24 34 40 44 45 55 60 70 > ? '''?'''
  33 KB (4,919 words) - 12:31, 21 June 2023

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