PDP-11 family differences appendix

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The PDP-11 Architecture Handbook (1983-84 version) contains a "PDP-11 Family Differences" appendix (re-printed in the MICRO/PDP-11 Handbook, 1983-84 version) which lays out in tabular form the few ways, and the models involved, which vary from each other in the fine details of their behavior. (Had DEC formalized the PDP-11 architecture earlier, these might not have happened, but once the products had made their way to customers, the die was cast.)

A few other minor inter-model differences (some well-documented, some not) have been discovered: they are given in a similar tabular form (with groups of rows for each idiosyncrasy) here:

Item 03 23/24 73/83/93 04 05 20 34 40 44 45 70
The SXT instruction clears the 'V' bit  % @ @ @ @ - @ @ @ @
SXT - 'V' bit unaffected - @
Blank SSR1 register -  % - - - - @ - - -
No SSR1 - - - - - @ - - -
Subset MMU with SSR3 register -  % - - - - - - -
No SSR3 - - - - - @ @ - - -
Explicit caching control per-segment - - @ - - - - -
Only global cache enable - - - - - @ - @ - @

An '@' indicates that the manuals for this CPU indicate that it operates in the manner stated; a '%' indicates that this behaviour has been confirmed by testing. A blank entry in both rows of the pair indicates that the behavior of this model is unknown; a '-' indicates that this model does not support that instruction, or is otherwise inapplicable.

The CPU models referred to in each of the columns above are:

Model CPU
03 LSI11 CPUs
23/24 KDF11 CPUs
73/83/93 KDJ11 CPUs
04 KD11-D CPU
05 KD11-B CPU
20 KA11 CPU
34 KD11-E CPU/KD11-EA CPU
40 KD11-A CPU
44 KD11-Z CPU
45 KB11-A CPU/KB11-D CPU/
70 KB11-B CPU/ KB11-C CPU/