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• Shift register
  ...rpose of the shift register. For instance, a shift register in a [[Central Processing Unit|CPU]], used for arithmetic purposes, would typically be both loaded an Another common use of a shift register is to take data being sent between two subsystems in serial form, using a single [[conducto
  1 KB (236 words) - 20:43, 4 August 2021
• Serial
  ...essing where one [[bit]] is handled at a time, with successive bits in any data item (such as a [[word]]) being handled in later time slots. ...and the [[arithmetic logic unit|ALU]] in a [[serial computer]]'s [[Central Processing Unit|CPU]], which would have only a single-bit adder, and to add two number
  688 bytes (116 words) - 23:28, 6 August 2021
• DV11 Communications Multiplexer
  ...[[flat cable]]s connect the main unit to each distribution panel (two for data and [[clock]], two for modem control.). ...different 16-[[bit]] [[instruction]]s (BRANCH A, BRANCH B, ALU OP, RAM OP, DATA XFR, NPR OP, SET/CLR OP, BCC OP), and an [[arithmetic logic unit|ALU]] buil
  6 KB (823 words) - 04:24, 18 February 2023
• International Network Working Group
  ...was given a formal home in the [[International Federation for Information Processing]], as IFIP Working Group 6.1 - Computer Communication.
  1 KB (185 words) - 18:10, 20 January 2024
• UNIBUS Device Addresses
  [[Central Processing Unit|CPU]] [[register]]s marked as "[[PDP-11/73|11/73]]" also appear in the | 777732 || Diagnostic Controller Data (11/84)
  7 KB (927 words) - 11:26, 12 November 2021
• Alto-1822 Interface
  ...[[Central Processing Unit|CPU]] bus, and used custom [[microcode]] to move data to and from [[main memory]]. It was [[full-duplex]], but included no [[buff
  3 KB (443 words) - 14:59, 21 May 2023
• DMA Request and Grant
  ...there; they are for a [[peripheral|device]] to gain control of the QBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. The [[Central Processing Unit|CPU]] may not perform ''any'' action (i.e. an [[interrupt]]) while the
  1 KB (197 words) - 19:37, 27 July 2024
• Datapoint 2200
  The base unit included a [[CPU|Central Processing Unit]], a small amount of [[main memory]], two digital cassette [[magnetic ...have an 8-bit [[operation code]], and an optional single byte of immediate data, or two bytes of [[address]].
  5 KB (814 words) - 20:05, 4 June 2023
• DW780 Unibus Adapter
  * M8272 - UBA Map and Data Path (UMD) ...a custom 6-slot [[backplane]] (normally mounted next to the main [[Central Processing Unit|CPU]] backplane). 2 slots (on the back of the backplane) are used to h
  2 KB (314 words) - 21:03, 15 May 2024
• KA780 CPU
  The '''KA780 CPU''' was the [[Central Processing Unit|CPU]] for the [[VAX-11/780]]. | 13 || M8229 || DAP || Data Path
  2 KB (259 words) - 00:08, 3 January 2022
• MA780 Multiport Memory Option
  * in each connected [[Central Processing Unit|CPU]] (between 2 and 4), an '''MA780-C Port Interface''', held in anot | 11 || M8212 || MDT || Memory Data Paths
  3 KB (487 words) - 14:56, 15 May 2024
• Synchronous Backplane Interconnect
  ...e high-speed [[bus]] which connected the major functional units ([[Central Processing Unit|CPU]], [[main memory]], [[Input/output|I/O]] adapters, etc), in early ...me other operation might use some of the slots before the one in which the data is returned.
  3 KB (455 words) - 17:09, 14 May 2024
• KK11-B Cache Memory
  ...D11-Z CPU]] of the [[PDP-11/44]], a high-speed [[cache]] for the [[Central Processing Unit|CPU]]. Each cache entry was 30 bits wide, containing two data bytes; also a tag field for cache entries, 9 bits wide (covering [[Extended
  3 KB (501 words) - 16:27, 6 February 2024
• KY11-J Programmer's Console
  ...in [[main memory]], and start, [[halt]] and [[single-step]] the [[Central Processing Unit|CPU]]. The 'Address/Data' indicator array display memory [[address]]es and data. The 'Run' light indicates that the CPU is [[execute|executing]] [[instruct
  2 KB (372 words) - 18:05, 25 January 2022
• KDJ11-D CPU
  ...KDJ11-D/S''' in the later variant (below), is the third [[QBUS]] [[Central Processing Unit|CPU]] card using the [[J-11 chip set]] of the [[PDP-11]] of the [[KDJ1 ...f the logic into two [[gate array]]s (DC7063 for control, and DC7064 for [[data path]]s), which made room for up to 1.5MB of memory.
  4 KB (657 words) - 16:09, 27 July 2024
• DEC Semiconductor Chips
  | NVAX Central Processing Unit [[#ref_25|[25]]] | F-11 Data [[#ref_1|[1]]][[#ref_30|[30]]]
  36 KB (3,420 words) - 05:36, 5 November 2022
• M7259 Parity Control Module
  ...is thus not supported for MM11-L/MM11-U units in a [[PDP-11/05]] [[Central Processing Unit|CPU]] backplane. On a read cycle, when the memory unit has put the data on the UNIBUS, it asserts that signal; on seeing it, the M7259 then generat
  4 KB (621 words) - 22:21, 6 July 2022
• KA750 CPU
  The '''KA750 CPU''' was the [[Central Processing Unit|CPU]] of the [[VAX-11/750]]. It was a [[synchronous]] [[microcode]]d d * L0002 Data Path Module (DPM) - arithmetical and logical functions, micro-sequencer
  3 KB (519 words) - 03:33, 18 May 2024
• KDF11-U CPU pinout
  ...mi-separate [[UNIBUS]], and [[Extended UNIBUS]] used between the [[Central Processing Unit|CPU]] and [[main memory]]; others are part of the connection between t | FN1 || K12-D4 || DATA TERM RDY 2
  8 KB (1,587 words) - 16:14, 6 February 2024
• CPU/Memory Interconnect
  ...he main [[bus]] which connects the main sub-systems (such as the [[Central Processing Unit|CPU]] and [[main memory]], as well as [[input/output|I/O]] adapters) i ...ns of the CMI are to do priority arbitration for use of the bus, and carry data between the sub-systems, as well as carrying [[interrupt]]s. It is also use
  3 KB (406 words) - 20:36, 18 May 2024

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