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• KA630 CPU
  {{InfoboxVAXCPU-Data The '''KA630''' is the [[Central Processing Unit|CPU]] used in [[Digital Equipment Corporation|DEC]]'s [[MicroVAX II]].
  2 KB (174 words) - 06:15, 28 June 2022
• Starlink
  ...anticipated flood of data in digital form which would be generated by new data acquisition techniques. In April 1978, SRC set up a Panel on Astronomical Image and Data Processing under the chairmanship of Professor Mike Disney to ascertain the computing
  1 KB (194 words) - 01:54, 20 December 2018
• Intel 8086
  ...16-bit CPU, which means the internal [[data bus]], along with the external data bus. ...hile it retained the same addressing modes, and instructions, the external data bus was 8 bits wide. The 8088 was the primary CPU found in the [[IBM 5150|
  1 KB (210 words) - 13:29, 3 November 2018
• Intel 80186
  ...tral Processing Unit|CPU]]. It also exists in an 80188 variant (with 8-bit data bus, like the [[Intel 8088]]).
  975 bytes (146 words) - 13:32, 3 November 2018
• Real Programmers Don't Use Pascal
  Real Programmers do List Processing in FORTRAN. ...ming language with all sorts of complications. The worst thing about fancy data types is that you have to declare them, and Real Programming Languages, as
  22 KB (3,770 words) - 14:23, 25 August 2021
• Linux 0.00
  # The third is the system of data # Register all of the data, all point system, gdt Table 3
  14 KB (1,991 words) - 01:23, 20 December 2018
• DZ11 asynchronous serial line interface
  ...grammed I/O]], and thus could present a considerable load on the [[Central Processing Unit|CPU]] when running a high speed line, using [[interrupt]]s. A 64-entry |Transmit Data Register || TDR || 760106
  5 KB (730 words) - 02:26, 19 February 2023
• Installing NetBSD 5.0.2 on the SIMH MicroVAX II
  # Based on the maketape.c program and the maketape.data data file. i: Text Processing Tools No
  8 KB (1,125 words) - 02:02, 18 November 2010
• NetBSD 0.9 announcement
  add delay loop to lpa and lpt drivers to allow data port fixed bug in ECHONL processing (andrew)
  29 KB (4,794 words) - 18:15, 16 December 2018
• DLV11-E asynchronous serial line interface
  ...ters for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser
  3 KB (489 words) - 01:18, 17 February 2023
• DLV11-J asynchronous serial line interface
  ...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h That line can be set to [[halt]] the [[Central Processing Unit|CPU]], or [[bootstrap|re-boot]] the system, when a '[[asynchronous ser
  4 KB (684 words) - 01:20, 17 February 2023
• DLV11 asynchronous serial line interface
  ...r]]s for the receive side (one Control and Status Register - CSR - and one data [[buffer]] register), and similarly, two for the transmit side. Each line h ...64-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when a '[[asynchronous serial line|break]]' is seen.
  2 KB (378 words) - 19:15, 7 July 2023
• TPA-11/580
  ...open architecture member of the KFKI TPA-family. With a microcoded central processing unit, the speed and performance is due to its efficient instruction set and ...lates the 30-bit SBI addresses to 18-bit UNIBUS addresses, handles DMA and data buffering (The UBA does 4 UNIBUS-cycles on one SBI cycle).
  4 KB (587 words) - 00:38, 2 January 2024
• UNIX V6 memory layout
  ...y simple. The [[operating system]]'s [[kernel]] (both [[instruction]]s and data) permanently occupies low physical memory; [[process]]es reside above the k ...for one or two (see below) large block(s) containing the kernel's code and data; details of the kernel's address space and main memory layout are given bel
  7 KB (1,161 words) - 15:20, 8 July 2023
• KD11-E/EA microcode
  ...PU]] provide nice [[flow chart]]s for the [[microcode]] in these [[Central Processing Unit|CPUs]]; with one tiny exception, the microcode in the two is identical | 026 || 9-I || 322 || Fetch index data
  31 KB (3,760 words) - 05:02, 5 November 2022
• INTEL 80386 PROGRAMMER'S REFERENCE MANUAL
  Above, BITBUS, COMMputer, CREDIT, Data Pipeline, FASTPATH, Genius, i, Œ, trademark. MDS(R) is a registered trademark of Mohawk Data Sciences
  890 KB (107,817 words) - 03:20, 3 January 2024
• IBM OS2 1.0 announcement
  o Concurrent Processing of Multiple Applications of memory beyond 640KB for applications and data. End users will
  50 KB (7,113 words) - 03:35, 17 December 2018
• Inside OS/2
  Library of Congress Cataloging in Publication Data British Cataloging in publication Data available
  627 KB (92,395 words) - 03:42, 17 December 2018
• User:Jnc
  [[Data path]] - [[Data bus]]
  47 KB (6,794 words) - 03:55, 18 May 2024
• LSI-11
  ...ped in the Fall of 1975, was DEC's first cost-reduced [[PDP-11]] [[Central Processing Unit|CPU]], introducing the [[QBUS]], and using the [[LSI-11 chip set]]. It ...component side facing the viewer) is [[KEV11]], μROM 1, μROM 0, Control, Data Path.
  3 KB (411 words) - 22:06, 20 December 2023

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