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- * G110 - [[DEC card form factor|hex-width]] memory control logic and data channels ...planes wired to hold one or more MM11-L sets, in addition to the [[Central Processing Unit|CPU]].5 KB (841 words) - 07:14, 25 March 2022
- The appropriate UNIBUS signal lines ([[address]], data, etc) were thus wired to the appropriate rows/pins in SPC slots. Other pins ...] and [[PDP-11/34]], on the [[DD11-P backplane]] which holds the [[Central Processing Unit|CPU]] card(s), along with the [[KY11-LB Programmer's Console]] (which5 KB (868 words) - 23:38, 9 April 2022
- It used four 4-bit wide [[PROM]]s to hold the data. The board occupied [[address]]es 773000-773776 and 765000-765776; a config Other configuration switches controlled which address the [[Central Processing Unit|CPU]] jumped to on power on (a clever kludge, controlled by another co9 KB (1,304 words) - 19:41, 7 December 2021
- The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' (' ...alled; they connect to the E Bus (for control), and also to the C Bus (for data movement). The [[MASSBUS]] can be used to connect a variety of [[disk]] and11 KB (1,737 words) - 13:06, 2 April 2024
- ...eripheral Controller|SPC]] slot in the same [[backplane]] as the [[Central Processing Unit|CPU]], and a 20-[[conductor]] [[flat cable]] which connected the two. ...d, a 6-digit [[Light Emitting Diode|LED]] display which showed address and data information, several individual indicator LEDs, and the following function7 KB (1,114 words) - 20:56, 24 October 2022
- .../70]] computers ([[KB11-A CPU|KB11-A]] and [[KB11-B CPU|KB11-B]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was the progenitor of the se * M8113 Exponent and Data Path1 KB (201 words) - 02:17, 13 October 2022
- ...uters (the later [[KB11-D CPU|KB11-D]] and [[KB11-C CPU|KB11-C]] [[Central Processing Unit|CPU]] variants thereof, respectively); it was [[program compatible]] w * M8129 Exponent and Data Path1 KB (209 words) - 02:18, 13 October 2022
- ...''KDJ11-B''' CPU board (M8190) is the second-generation [[QBUS]] [[Central Processing Unit|CPU]] card using the [[J-11 chip set]] of the [[PDP-11]] (the first be ...o errors, even with the switches set to 000300Q for extended cache tag and data RAM tests. After entering field service mode in '''VMJAB0''' and disabling6 KB (1,052 words) - 22:52, 26 July 2024
- ...roduced with the [[KDJ11-B CPU]]. It also provides means for the [[Central Processing Unit|CPU]] and a [[KTJ11-B UNIBUS adapter|KTJ11-B]] [[UNIBUS]] adapter to c ...[main memory]], PMI provides two primary modes; i) single- and double-word data reads, and single-word and single-byte writes; ii) block mode, which can re4 KB (731 words) - 17:11, 6 February 2024
- ...although only a maximum of 64 KBytes is accessable (i.e. in the [[Central Processing Unit|CPU]]'s address space) at any one time. ...anently dedicating scarce memory space in the Exec's address space to such data, or ii) having to change a number of page table entries in the Exec mode pa15 KB (2,571 words) - 22:23, 11 October 2022
- The [[Central Processing Unit|CPU]] can be in one of three modes; 'Kernel', 'Supervisor', and 'User' An additional enhancement is that [[instruction]] and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called9 KB (1,320 words) - 19:20, 27 July 2024
- ...visible to to user as first-class objects, are supported in the [[Central Processing Unit|CPU]] (in the [[instruction]]s), etc; whereas pages are generally invi ...t size, measured in small units, is often stored in a field as part of the data which describes the segment to the CPU's hardware), whereas with variable p5 KB (876 words) - 20:01, 22 January 2024
- The '''KA11''' is the [[Central Processing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]]. It was the only PDP- * [[Data path|Data Paths]]9 KB (1,356 words) - 23:10, 29 February 2024
- ...[[register]] names must be known, as well as the function of the [[Central Processing Unit|CPU]] and [[peripheral|device]] [[UNIBUS]]es, and also high-level inte [[Image:KT11-B_DataPaths.jpeg|450px|right|Main data paths]]31 KB (4,983 words) - 18:22, 2 July 2023
- There are several single-board [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Jaws' [[J-11 chipset]]: ...even if that memory location is faulty - the CPU is getting the (correct) data from the cache.3 KB (457 words) - 14:32, 21 February 2023
- ...P-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Processing Unit|CPU]] was implemented in two [[integrated circuit|chips]] (carried on ...although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)2 KB (384 words) - 23:50, 28 March 2022
- The '''Central Processing Unit''', usually abbreviated as '''CPU''', or simply called a '''processor' Instructions include data-handling instructions (such as arithmetic and logical operations), and cont1 KB (196 words) - 13:14, 5 November 2023
- ...ion (the 'Control Bus'), and a [[synchronous]] data transfer section (the 'Data Bus'). The two sections operate completely independently. ...sing Unit|CPU]] access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bi5 KB (729 words) - 21:36, 2 December 2023
- Instructions in the LINC [[Central Processing Unit|CPU]] could seek to a given block, and then read or write multiple blo The tape contained timing and mark tracks along with three data tracks; the first two allowed not only the ability to re-write individual b3 KB (519 words) - 02:13, 28 February 2024
- ...a [[Direct Memory Access|DMA]] peripheral to the PDP-8, using the PDP-8 [[data break]] mechanism). A combined [[front panel]] allowed control of both CPUs2 KB (328 words) - 13:46, 11 July 2023