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• Berkeley Time-Sharing System
  ...rating modes for the [[CPU]], "user" and "monitor" (or "executive") to the base "normal" mode (in which the machine operated ''almost'' exactly as a normal * The user's [[address space]] was divided into 8 [[segment]]s (each 2K [[word]]s long), each of w
  4 KB (603 words) - 14:51, 11 June 2023
• Swapping
  '''Swapping''' is the term for moving the contents of a [[process]]' [[address space]], as a unitary entity, back and forth between [[main memory]] and [[ ...did not support paging, i.e. those which did [[memory management]] using [[base and bounds]] [[register]]s.
  1 KB (185 words) - 21:38, 15 December 2018
• Array
  ...ed to the index (often through use of an [[index register]]) to give the [[address]] of the desired array element.
  681 bytes (105 words) - 16:21, 15 December 2018
• Term-Mite ST Smart Terminal/TermMite.asm
  mov home,a ;home address = 0000 (this changes with scrolling) L0133 mov a,#10H ;move 1000 to cursor address
  24 KB (5,539 words) - 03:05, 27 December 2018
• PARC Universal Packet
  In the 1980s [[Xerox]] used PUP as the base for the [[Xerox Network Services]] (XNS) protocol suite; some of the protoc ...ds to the [[Internet Protocol]] (IP) layer in TCP/IP. A full PUP [[network address]] consisted of an 8-bit network number, an 8-bit host number, and a 16-bit
  6 KB (926 words) - 16:27, 11 May 2023
• CDC 6600
  | physical address = 17 bits | memory mgmt = [[base and bounds]]
  6 KB (789 words) - 17:26, 22 January 2024
• IBM 7030 Stretch
  | physical address = 18 bits (256K words) | virtual address = 18 bits
  3 KB (467 words) - 16:37, 11 January 2024
• Mapping
  ...]]es in physical [[main memory]]. This may be done in a simple way, with [[base and bounds]] [[register]]s, or the use of [[page table]]s when [[virtual me
  483 bytes (74 words) - 19:33, 14 December 2018
• KL11 Teletype Control
  ...SPC]] slot, along with two standard single card [[FLIP CHIP]]s, the [[M105 Address Selector]] and the [[M782 Interrupt Control]]. ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector.
  3 KB (400 words) - 16:21, 18 February 2023
• KEV11-C Commercial Instruction Set
  ...cause the DIS and basic [[instruction set]] together use the entire uROM [[address space]]. ...40-pin hybrid (two chips on one carrier) which holds the two uROMs of the base instruction set. The hybrid is 23-001B6, 23-002B6, or 23-003B6 (for M7264 E
  1 KB (241 words) - 21:11, 2 July 2023
• LSI-11 chip set
  | 22-23 || x ||   || [[Bus Address Register|BAR]] ...codes]] logic, and a data port which gives access to the [[QBUS]]' data/[[address]] lines.
  5 KB (773 words) - 22:42, 20 December 2023
• UNIX V6 dump analysis
  ...est (typing '^\' in standard V6), or by any of the error conditions (odd [[address]], etc) which cause a process abort and core dump. ...either kind), they are not contiguous in the process [[virtual address]] [[address space|space]]; the [[PDP-11 Memory Management]] separates them there.
  4 KB (719 words) - 12:07, 2 July 2022
• KD11-K CPU
  It was a microcoded CPU, using 48-bit wide micro-words; the [[address space]] of the micro-engine was 2¹² words, divided into 8 blocks <li>Base instructions</li>
  4 KB (536 words) - 12:34, 11 October 2022
• MG10 core memory
  ...trollers', with the controller used for any particular cycle selected by [[address]] bit 21. ...or to be disabled. The base address of an MG10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
  2 KB (342 words) - 12:33, 5 November 2023
• MH10 core memory
  ...trollers', with the controller used for any particular cycle selected by [[address]] bit 20. ...y enabled/disabled. The base address of an MH10 is switch-selectable; that address is used on all the ports, unlike the earlier [[PDP-10 memories]].
  3 KB (407 words) - 12:40, 5 November 2023
• Systems Concepts DK-10
  | colspan=15 | Unused || IE || colspan=20 | Base address The base address specifies a region in physical memory holding a word pair for each line. T
  2 KB (311 words) - 15:15, 24 October 2022
• DLV11-F asynchronous serial line interface
  ...egisters are 0777560-2, and the transmitter are 0777564-6), and 060 is the base vector. It can be set to [[halt]] the [[Central Processing Unit|CPU]] when The first line after the console is always assigned the address 0776500, and vector 0300. Additional lines are assigned addresses and vecto
  3 KB (469 words) - 01:19, 17 February 2023
• DM11 Asynchronous 16-line Single-Speed Multiplexer
  * per-line current output [[buffer]] [[address]] ! Register !! Abbreviation !! Address
  8 KB (1,088 words) - 02:24, 19 February 2023
• KA650 Main Memory System
  ...E pin. Also available to the RAM card are the inverse of the 20th and 21st address lines (XA20 & XA21), which are used as bank selection when using 256kxX DRA ...y the row address on the rising edge of a RAS line, followed by the column address on the rising edge of a CAS line.
  42 KB (5,493 words) - 15:53, 23 May 2024
• 3Com 3C501
  I/O BASE ADDRESS SELECTION ! style="text-align:left;"| Address
  2 KB (316 words) - 15:15, 24 April 2024

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