KD11-A CPU
The KD11-A PDP-11 CPU for the PDP-11/35 and PDP-11/40 was a multi-board micro-programmed processor.
Support for the EIS was optional, with the KE11-E Extended Instruction Set, a hex card. There was also optional floating point hardware, the KE11-F Floating Instruction Set, a quad card; it was not the full FP11 Floating Point, but the minimal FIS floating point.
Memory management support was also optional, with the KT11-D Memory Management, another hex card; it too was not the full PDP-11 Memory Management, but the simplified subset.
Other CPU options included the KJ11-A Stack Limit Register, and the KW11-L Line Time Clock (the latter being a standard option across a number of PDP-11 CPUs).
Implementation
The basic KD11-A was contained on four hex cards:
- M7231 - Data Paths
- M7233 - IR Decode
- M7234 - Timing
- M7235 - Status
and one quad card:
- M7232 - μword
The Berg connectors on the M7232 carry the microcode bus to the KE11-E EIS card; note also the metal handle on this card, even though it is only a quad card; the only non-QBUS quad card with such a handle.
All of them plugged into a wire-wrapped custom backplane dual system unit. The KE11-E Extended Instruction Set, KE11-F Floating Instruction Set, and KT11-D Memory Management option cards all plugged into pre-wired slots in this backplane, as did the KJ11-A Stack Limit Register and the KW11-L Line Time Clock.
