KDJ11 PMI/UNIBUS backplane
The KDJ11 PMI/UNIBUS backplane, H9277-A (DEC part number 70-20650-01), is used with the KTJ11-B UNIBUS adapter, along with the KDJ11-B and KDJ11-E QBUS CPU cards, to provide UNIBUS capability to systems built around those CPU cards; the PDP-11/84 and PDP-11/94 systems respectively.
Backplane details
The custom 12+1 slot backplane used with the KDJ11-B/E and KTJ11-B was half Private Memory Interconnect (PMI; a variant of the QBUS), and half UNIBUS (the 13th 'slot' is not a full slot, it only has a connector for one set of fingers). It has PMI bus slots at the top (for the CPU and main memory cards), a special slot in the middle for the KTJ11-B, and then UNIBUS slots.
In detail, the backplane contains (in order) four quad-height slots, the first of which is the custom partial slot, and the others are PMI (technically Q22/CD, although slightly modified from the normal form of that in this backplane, see below); they are used for (in order, from the front of the machine):
- the Machine Debug Monitor board (M7677); this slot is not numbered
- the CPU board; this is slot 1
- main memory board
- optional second main memory board
and nine hex-height slots, used for:
- KTJ11-B UNIBUS adapter, in slot 4
- four SPC UNIBUS slots
- three MUD UNIBUS slots
- UNIBUS 'out' and quad SPC slot, in slot 12
Note that the PMI slots do not have the bottom-up ordering of PMI-capable slots in a Q22/CD backplane, but are wired as a true bus (fully interconnected), allowing the 'CPU, memory, memory' insertion ordering seen here.
Note also that in the normal configuration (see below for details), the QBUS bus grant lines are not routed through the memory slots, so if one of these slots is unused, there is no need for a M9047 grant continuity card in that slot.
As a further feature, on most UNIBUS backplanes, the 'NPG' (DMA grant line) signal is carried across unused slots by wire jumpers on wire-wrap pins on the back side of the backplane; on the -11/84 backplane, they are brought out to a DIP switch on the MDM module, for easier configuration changes.
Any UNIBUS slot which does not have a device installed in it, must have a grant continuity card such as a G7273 placed in it.
Backplane layout
Board locations are:
| Connector | ||||||
|---|---|---|---|---|---|---|
| Slot | A | B | C | D | E | F |
| 0 | M7677 MDM | |||||
| 1 | M8190 or M8981 CPU | |||||
| 2 | PMI memory | |||||
| 3 | PMI memory | |||||
| 4 | M8191 UBA | |||||
| 5 | SPC device | |||||
| 6 | SPC device | |||||
| 7 | SPC device | |||||
| 8 | SPC device | |||||
| 9 | MUD device | |||||
| 10 | MUD device | |||||
| 11 | MUD device | |||||
| 12 | UNIBUS Out | SPC device | ||||
Note: In an -11/94, there will usually be no PMI memory, but there will be an M9714 Alternate Power Source card in connectors A-B of slot 2.
QBUS slots
The two main memory slots can in fact be configured as regular Q22/CD QBUS slots, by removing two jumpers. EK-PDP84-TM-PR4 (PDP-11/84 Technical Manual) says (in section 2.1.14, "Backplane (H9277-A)", pg. 2-6):
- Bus signals BDMGI (pin AR2) and BIAKI (pin AM2) for slots 2 & 3 are jumpered on the front of the backplane.
There are indeed two jumpers, W1 and W2 (in the upper right-hand corner, when facing the backplane from the board insertion side); the traces connected to them are on the surface, so it is possible to see where they go: one end runs to a trace connected from slot 1 to slot 2, and the other to a trace connected from slot 3 to slot 4; those connect to AM2 (BIAKI) and AN2 (BIAKO), and AR2 (BDMGI) and AS2 (BDMGO).
Thus, when the jumpers are in, the CPU's BIAKO/BDMGO pins are connected directly to the UNIBUS adapter's BIAKI/BDMGI pins; when they are out, those signals are routed through the two 'memory' slots, in the normal QBUS manner.
It therefore seems those two slots might be able to function as real QBUS slots. However, it is not clear that the CPU will 'do the right thing'; the UNIBUS adapter puts out a signal to let the CPU know that it is there, and the CPU may then expect to see only PMI-type DMA and interrupt cycles on the bus.
The DMA cycle might work, it all depends on what happens at step 8 (EK-KDJ1B-UG-001, pp. 7-6 to 7-9) when, instead of PBSY being asserted, BSYNC is asserted. The PMI memory will be fine (since in an -11/83, this kind of thing is expected)... but the CPU, who knows. (The CPU would do the right thing in an -11/83, but the same board might not do the right thing here, since it 'knows' there is a UNIBUS adapter present.)
Interrupt cycles are more problematic; the assertion of the interrupt level on the BDAL lines (step 1a) will probably pass, but step 6 (assertion of BSACK) may be an issue, since the device will want to assert BRPLY instead (BSACK is not used in a QBUS interrupt), and the CPU may not do the right thing.
External links
- PDP-11/84 System Technical and Reference Manual (EK-1184E-TM-001)
- PDP-11 Systems Handbook (EB 29317 41) - the overall architecture that the H9277-A implements is covered on pp. 127-129 of the PDF
- 11/84 Field Maintenance Print Set (MP-02015-001) - the H9277-A is covered on pp. 16-22 of the PDF
