Difference between revisions of "DS11 Multiple Line Synchronous Interface"

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(Add implementation details - board types)
(Add ISR, reg contents)
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|-
 
|-
 
|Transmitter Data Buffer Register          || TxDBUF || 775xx6
 
|Transmitter Data Buffer Register          || TxDBUF || 775xx6
 +
|-
 +
|Interface Status Register                || ISTR || 775600
 
|}
 
|}
  
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: ...
 
: ...
 
* Line 15: 775570-775576
 
* Line 15: 775570-775576
<!--
+
 
===16xx10: Receiver Status Register (RxCSR)===
+
In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in ''italics'', and write-only in '''bold'''.
 +
 
 +
===175xx0: Receiver Status Register (RxCSR)===
  
 
{{16bit-header}}
 
{{16bit-header}}
| DSC || RING || CTS || CARR || RACT || SECRCV || DSR || STRSYN || RDN || RIE || DSIE || SRCHSYN || SECXMT || RTS || DTR || Unused
+
| RING || BITOVR || CHAROVR || CARLST || colspan=2 | SYNCST || ''CARDET'' || DTR || ''DONE'' || ''DSR'' || colspan=2 | CHARLEN || colspan=2 | DNIA || RNGENB || RCVENB
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
* DSC - Data Set Change; set for any change on Ring, Carrier, Data Set Ready, Clear to Send or Secondary Received Data lines
+
* BITOVR - Bit Overrun
* RING - Ring Indicator
+
* CHAROVR - Character Overrun
* CTS - Clear to Send
+
* CARLST - Carrier Lost
* CARR - Carrier
+
* SYNCST - Sync State
* RACT - Receiver Active; setting dependent on the internal/external synchronization mode
+
* CARDET - Carrier Detected
* SECRCV - Secondary Received Data
+
* DTR - Data Terminal Ready
 
* DSR - Data Set Ready
 
* DSR - Data Set Ready
* STRSYN - Strip Sync; sync characters are discarded
+
* CHARLEN - Character Length
* RDN - Receive Done Flag; set  when the receive buffer is filled with an assembled character
+
* DNIA - Done Interrupt Assignment
* RIE - Receiver Interrupt Enable; allows an input interrupt when Receive Done is set
+
* RNGENB - Ring Enable
* DSIE - Data Set Interrupt Enable; allows an input interrupt when DSC is set
+
* RCVENB - Receiver Enable
* SRCHSYN - Search Synchronization; when set, the receiver looks for synch character(s)
 
* SECXMT - Secondary Transmit Data
 
* RTS - Request to Send
 
* DTR - Data Terminal Ready
 
  
===16xx12 (read): Receiver Data Buffer Register (RxDBUF)===
+
===175xx2 (read): Receiver Data Buffer Register (RxDBUF)===
  
 
{{16bit-header}}
 
{{16bit-header}}
| ERR || OVR || Unused || PARERR || colspan=4 | Unused || colspan=8 | RDBUF
+
| colspan=4 | Unused || colspan=12 | RDBUF
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
* ERR - Error
 
* OVR - Overrun
 
* PARERR - Parity Error
 
 
* RDBUF - Receiver Data Buffer
 
* RDBUF - Receiver Data Buffer
  
===16xx12 (write): Parameter Control Register (PARCSR)===
+
===175xx4: Transmitter Status Register (TxCSR)===
  
 
{{16bit-header}}
 
{{16bit-header}}
| colspan=2 | Unused || colspan=2 | MODE || colspan=2 | LEN || PAR EN || EVEN PAR ||  colspan=8 | SYNC
+
| Unused || BITOVR || CHAROVR || CTSLST || colspan=2 | Unused || ''CTS'' || DTR || DONE || ''DSR'' || colspan=2 | CHARLEN || colspan=2 | DNIA || IDLE || RTS
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
* MODE - Synchronous Mode Select (10=External, 11=Internal)
+
* BITOVR - Bit Overrun
* LEN - Length (00=5, 01=6, 10=7, 11=8)
+
* CHAROVR - Character Overrun
* PAR EN - Parity Enable
+
* CTSLST - Clear to Send Lost
* EVEN PAR - Even Parity selected
+
* CTS - Clear to Send
* SYNC - Sync Character
+
* DTR - Data Terminal Ready
 +
* DSR - Data Set Ready
 +
* CHARLEN - Character Length
 +
* DNIA - Done Interrupt Assignment
 +
* RTS - Request to Send
  
===16xx14: Transmitter Status Register (TxCSR)===
+
===175xx6: Transmitter Data Buffer Register (TxDBUF)===
  
 
{{16bit-header}}
 
{{16bit-header}}
| DNA || MD || MCLK || colspan=2 | MMS || MBW || Unused || MR || TDN || TIE || DNAIE || SEND || HDFD || colspan=2 | Unused || BRK
+
| colspan=4 | Unused || colspan=12 | TDBUF
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
* DNA - Data Not Available
+
* TDBUF - Transmitter Data Buffer
* MD - Maintenance Data
 
* MCLK - Maintenance Clock
 
* MMS - Maintenance Mode Select (01=Internal, 10=External, 11=Internal systems)
 
* MBW - Maintenance Bit Window
 
* MR - Master Reset
 
* TDN - Transmitter Done; set when the Transmitter Data Buffer is ready for the next character
 
* TIE - Transmitter Interrupt Enable; allows a transmit interrupt when Transmit Done is set
 
* DNAIE - Data Not Available Interrupt Enable
 
* SEND - Send; enables the transmitter logic
 
* HDFD - Half-Duplex/Full-Duplex
 
* BRK - Send [[Asynchronous serial line|Break]]
 
  
===16xx16: Transmitter Data Buffer Register (TxDBUF)===
+
===175600: Interface Status Register (ISTR)===
  
 
{{16bit-header}}
 
{{16bit-header}}
| colspan=8 | Unused || colspan=8 | TDBUF
+
| ''A3IN'' || ''A2IN'' || ''A1IN'' || colspan=3 | Unused || colspan=2 | VAHBITS || DIAGM || PRCLK || Unused || '''CLRBC''' || colspan=4 | ''DIAGBC''
 
{{16bitoctal-bitout}}
 
{{16bitoctal-bitout}}
  
* TDBUF - Transmitter Data Buffer
+
* A3IN - Adapter 3 In
 +
* A2IN - Adapter 2 In
 +
* A1IN - Adapter 1 In
 +
* VAHBITS - Vector Address High Bits
 +
* DIAGM - Diagnostic Mode
 +
* PRCLK - Program Clock
 +
* CLRBC - Clear Bit Counter
 +
* DIAGBC - Diagnostic Bit Counter
  
-->
 
 
==Implementation==
 
==Implementation==
  

Revision as of 04:54, 5 January 2024

The DS11 Multiple Line Synchronous Interface was an early synchronous serial line interface for the UNIBUS; it could handle up to 16 lines. It used programmed I/O (with separate receive and transmit interrupts) to transfer data; it could operate in either half-duplex or full-duplex mode.

Character lengths of 6, 8 and 12 bits were supported, and could be configured by software. It provided an EIA RS-232 interface to Bell 200 series modems (such as the model 201, and equivalents), and also connect to Bell 300 series modems, such as the model 303.

Registers

Register Abbreviation Address
Receiver Status Register RxCSR 775xx0
Receiver Data Buffer Register RxDBUF 775xx2
Transmitter Status Register TxCSR 775xx4
Transmitter Data Buffer Register TxDBUF 775xx6
Interface Status Register ISTR 775600

Line addresses:

  • Line 0: 775400-775406
...
  • Line 15: 775570-775576

In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics, and write-only in bold.

175xx0: Receiver Status Register (RxCSR)

RING BITOVR CHAROVR CARLST SYNCST CARDET DTR DONE DSR CHARLEN DNIA RNGENB RCVENB
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • BITOVR - Bit Overrun
  • CHAROVR - Character Overrun
  • CARLST - Carrier Lost
  • SYNCST - Sync State
  • CARDET - Carrier Detected
  • DTR - Data Terminal Ready
  • DSR - Data Set Ready
  • CHARLEN - Character Length
  • DNIA - Done Interrupt Assignment
  • RNGENB - Ring Enable
  • RCVENB - Receiver Enable

175xx2 (read): Receiver Data Buffer Register (RxDBUF)

Unused RDBUF
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • RDBUF - Receiver Data Buffer

175xx4: Transmitter Status Register (TxCSR)

Unused BITOVR CHAROVR CTSLST Unused CTS DTR DONE DSR CHARLEN DNIA IDLE RTS
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • BITOVR - Bit Overrun
  • CHAROVR - Character Overrun
  • CTSLST - Clear to Send Lost
  • CTS - Clear to Send
  • DTR - Data Terminal Ready
  • DSR - Data Set Ready
  • CHARLEN - Character Length
  • DNIA - Done Interrupt Assignment
  • RTS - Request to Send

175xx6: Transmitter Data Buffer Register (TxDBUF)

Unused TDBUF
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • TDBUF - Transmitter Data Buffer

175600: Interface Status Register (ISTR)

A3IN A2IN A1IN Unused VAHBITS DIAGM PRCLK Unused CLRBC DIAGBC
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • A3IN - Adapter 3 In
  • A2IN - Adapter 2 In
  • A1IN - Adapter 1 In
  • VAHBITS - Vector Address High Bits
  • DIAGM - Diagnostic Mode
  • PRCLK - Program Clock
  • CLRBC - Clear Bit Counter
  • DIAGBC - Diagnostic Bit Counter

Implementation

The DS11 consisted of a master line scanner, and up to four adapters, each of which could handle up to four lines; each line had a separate quad M7110 Line Control Module. Physically, it is a large quad-height backplane, mounted in a 19" cabinet such as an H950, along with the DS11's DEC indicator panel.

The DS11, like some other early UNIBUS peripherals, was made of many small FLIP CHIPs. The inventory of the card types in the DS11 is:

  • G830 5V, 10A Regulator from 8V
  • M002 Resistor network
  • M126 6 x AND-NOR Gates
  • M128 4,4 AND-NOR Gates
  • M139 3 x 8-Input NAND Gates
  • M143 10 x 2-Input NAND Gates
  • M145 7 x 3-Input NAND Gates
  • M147 5 x 4-Input, 1 x 2-Input NAND Gates
  • M152 Dual Non-inverting Binary to Octal with Enable
  • M165 Memory buffer, Inverting and Non-inverting Output
  • M171 2-2-2-3 AND-NOR
  • M173 10 x 2-input AND gates
  • M174 4 En x 9 out mixer
  • M175 7 x 3-input AND gates
  • M177 5 x 4-Input AND Gates
  • M178 8 En x 6 out mixer
  • M181 Non-inverting 2-2-2-3 AND-NOR
  • M211 6-Bit Up/Down Counter
  • M241 6 x D Flip-flops with common clock
  • M243 8 x D Flip-flops with 2 common clocks
  • M246 5 x D Flip-Flops
  • M253 16 Word, 12-bit Memory
  • M307 Integrating One Shot
  • M321 Tapped Delay Line
  • M362 Delay, 25 to 50 ns
  • M401 Variable Clock
  • M603 Pulse Amplifiers
  • M612 6 Power Gates
  • M783 UNIBUS Drivers
  • M784 UNIBUS Receiver
  • M785 UNIBUS Transceiver
  • M931 15 Terminators
  • M969 24 Level Terminators
  • M511 UNIBUS Receivers - sources differ as to whether or not this is used
  • W990 Connectors
  • M105 Address Selector - used to set its bus address
  • M7820 Interrupt Control
  • M7110 Line Control Module - one per line

The number of each type used is currently unknown; likewise the locations in the backplane (except the M7110's)

See also

Further reading

  • DS11 Multiple Line Synchronous Interface Maintenance Manual (DEC-00-DS11-DB; not available online, but in fiche)

External links