Difference between revisions of "KDJ11 CPUs"
(Add NXM from PARs) |
m (KDJ11-B also used in the PDP-11/73) |
||
| (11 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
There are several single-board [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Jaws' [[J-11 chipset]]: | There are several single-board [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Jaws' [[J-11 chipset]]: | ||
| − | *[[KDJ11-A CPU]] - M8192 - [[QBUS]] [[DEC card form factor|dual]]-width CPU | + | * [[KDJ11-A CPU]] - M8192 - [[QBUS]] [[DEC card form factor|dual]]-width CPU |
| − | *[[KDJ11-B CPU]] - M8190 - QBUS quad-width CPU used in the [[PDP-11/83]] and [[PDP-11/84]] | + | * [[KDJ11-B CPU]] - M8190 - QBUS quad-width CPU used in the [[PDP-11/73]], [[PDP-11/83]] and [[PDP-11/84]] |
| − | *[[KDJ11-E CPU]] - M8981 - QBUS quad-width CPU used in the [[PDP-11/93]] and [[PDP-11/94]] | + | * [[KDJ11-D CPU]] - M7554 - QBUS quad-width CPU used in the [[PDP-11/53]] |
| + | * [[KDJ11-E CPU]] - M8981 - QBUS quad-width CPU used in the [[PDP-11/93]] and [[PDP-11/94]] | ||
==Floating point== | ==Floating point== | ||
| − | All the KDJ11 CPUs except early revisions of the KDJ11-A CPU have two choices for [[floating point]] support (full [[FP11 floating point]]): the base DCJ11 chip, which implements floating point using [[microcode]]; and an optional | + | All the KDJ11 CPUs except early revisions of the KDJ11-A CPU and the KDJ11-D have two choices for [[floating point]] support (full [[FP11 floating point]]): the base DCJ11 [[integrated circuit|chip]], which implements floating point using [[microcode]]; and an optional, higher-performance separate dedicated chip, the [[FPJ11 floating point accelerator]]. |
| − | (The issue with the KDJ11-A is that early revisions have bugs in their [[gate array]] | + | (The issue with the early KDJ11-A is that early revisions have bugs in their [[gate array]] chips which prevent correct operation of the FPJ11.) |
| − | ==ODT== | + | ==ODT and the cache== |
| − | The J-11 chip set includes | + | The J-11 chip set includes microcode which provides '[[front panel]]' functionality named '[[QBUS CPU ODT|ODT]]', which runs when the CPU is [[halt]]ed: the ability to read and write to [[main memory]], start the processor, etc. Unlike the ODT in the [[KDF11 CPUs]], which only supported 18-bit addressing, the KDJ11's do not have this limitation. |
| − | Note, however, that the KDJ11-A and KDJ11-B | + | Note, however, that the KDJ11-A and KDJ11-B, which have CPU [[cache]]s, power up with the cache enabled, even for ODT. So, if the user writes some data into a given memory location using ODT, and then reads it back, they will get the correct data even if that memory location is faulty - the CPU is getting the (correct) data from the cache. |
| − | To have 'memory' reads and writes actually go to the memory, the cache has to be turned off: | + | To have 'memory' reads and writes actually go to the memory on these two models, the cache has to be turned off: |
17777746/ 02000 | 17777746/ 02000 | ||
| Line 27: | Line 28: | ||
(It is not clear why there are two different ways to disable the cache.) | (It is not clear why there are two different ways to disable the cache.) | ||
| − | Note that starting the machine | + | Note that starting the machine, in ODT, again enables the cache. |
==Code in PARs== | ==Code in PARs== | ||
| − | One commonly used diagnostic 'trick' is to store very small test programs in the Page Address Registers of the [[PDP-11 Memory Management]] unit. This is typically used for short 'oscilliscope loops', either to debug a memory card when isn't any working memory plugged in, or when there is a desire to avoid 'contaminating' the bus with [[instruction]] fetch cycles. | + | One commonly used diagnostic 'trick' is to store very small test programs in the Page Address Registers of the [[PDP-11 Memory Management]] unit. This is typically used for short 'oscilliscope loops', either to debug a memory card when there isn't any working memory plugged in, or when there is a desire to avoid 'contaminating' the bus with [[instruction]] [[fetch]] cycles. |
However, this does not work on the KDJ11 processors. The CPU cannot execute [[object code|code]] from the PARs; it gets a [[NXM]] [[trap]] on attempts to do so. | However, this does not work on the KDJ11 processors. The CPU cannot execute [[object code|code]] from the PARs; it gets a [[NXM]] [[trap]] on attempts to do so. | ||
| + | |||
| + | ==See also== | ||
| + | |||
| + | * [[LSI-11 CPUs]] | ||
| + | * [[KDF11 CPUs]] | ||
==Further reading== | ==Further reading== | ||
| Line 39: | Line 45: | ||
* uNote #025, "FPJ11-AA Compatibility with the LSI-11/73 (KDJ11-A)", 28 April 1985 | * uNote #025, "FPJ11-AA Compatibility with the LSI-11/73 (KDJ11-A)", 28 April 1985 | ||
| − | + | ==External links== | |
| + | |||
| + | * [http://web.frainresearch.org:8080/projects/pdp-11/dcj11.php DCJ11 Processors] | ||
| − | [[Category: PDP-11 | + | [[Category: PDP-11 QBUS Processors]] |
| − | |||
Latest revision as of 14:32, 21 February 2023
There are several single-board PDP-11 CPUs which all use the 'Jaws' J-11 chipset:
- KDJ11-A CPU - M8192 - QBUS dual-width CPU
- KDJ11-B CPU - M8190 - QBUS quad-width CPU used in the PDP-11/73, PDP-11/83 and PDP-11/84
- KDJ11-D CPU - M7554 - QBUS quad-width CPU used in the PDP-11/53
- KDJ11-E CPU - M8981 - QBUS quad-width CPU used in the PDP-11/93 and PDP-11/94
Contents
Floating point
All the KDJ11 CPUs except early revisions of the KDJ11-A CPU and the KDJ11-D have two choices for floating point support (full FP11 floating point): the base DCJ11 chip, which implements floating point using microcode; and an optional, higher-performance separate dedicated chip, the FPJ11 floating point accelerator.
(The issue with the early KDJ11-A is that early revisions have bugs in their gate array chips which prevent correct operation of the FPJ11.)
ODT and the cache
The J-11 chip set includes microcode which provides 'front panel' functionality named 'ODT', which runs when the CPU is halted: the ability to read and write to main memory, start the processor, etc. Unlike the ODT in the KDF11 CPUs, which only supported 18-bit addressing, the KDJ11's do not have this limitation.
Note, however, that the KDJ11-A and KDJ11-B, which have CPU caches, power up with the cache enabled, even for ODT. So, if the user writes some data into a given memory location using ODT, and then reads it back, they will get the correct data even if that memory location is faulty - the CPU is getting the (correct) data from the cache.
To have 'memory' reads and writes actually go to the memory on these two models, the cache has to be turned off:
17777746/ 02000
or
17777746/ 014
(It is not clear why there are two different ways to disable the cache.)
Note that starting the machine, in ODT, again enables the cache.
Code in PARs
One commonly used diagnostic 'trick' is to store very small test programs in the Page Address Registers of the PDP-11 Memory Management unit. This is typically used for short 'oscilliscope loops', either to debug a memory card when there isn't any working memory plugged in, or when there is a desire to avoid 'contaminating' the bus with instruction fetch cycles.
However, this does not work on the KDJ11 processors. The CPU cannot execute code from the PARs; it gets a NXM trap on attempts to do so.
See also
Further reading
- uNote #025, "FPJ11-AA Compatibility with the LSI-11/73 (KDJ11-A)", 28 April 1985
