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The MASSBUS was a high-speed I/O bus devised by DEC, and used to connect DEC systems to high-speed disk drives and tape controllers such as the RP04, RP06, TM02 and TM03.

Two major goals of using a common I/O bus were:

The basic concept was suggested by Gordon Bell in July, 1972, and a committee of DEC engineers was formed to produce the first version of the specification, which came out in August.

The fact that the MASSBUS connects to disk drives and tape controllers causes terminological difficulties, since there is also a 'controller' to connect the MASSBUS to the host computer. Hence, the term 'device' will be used in this article to refer, generically, to things connected to the MASSBUS (other than the controller in the host system). A single MASSBUS can contain up to 8 devices.

A variety of controllers existed to connect a MASSBUS to various kinds of DEC systems: the RH10 for the PDP-10, the RH20 for the KL10, the RH11 for the UNIBUS (usually on a PDP-11), the RH70 for the PDP-11/70, the RH750 for the VAX-11/750, and the RH780 for the Synchronous Backplane Interconnect bus found on VAX-11/78x, VAX 86xx, etc.

The PDP-15 could also connect to MASSBUS devices via the UC15 Unichannel, but this used a PDP-11/05 acting as a slave to the PDP-15 via shared memory, and also an RH11 on the -11/05's UNIBUS.

In the MASSBUS system, most device-specific registers (e.g. 'current cylinder' for disk drives) are actually in the device; the MASSBUS interface to the host computer only contains registers such as main memory transfer address and transfer word counts.

Internal details

The MASSBUS contained two separate sections (effectively, separate busses): an asynchronous control section (the 'Control Bus'), and a synchronous data transfer section (the 'Data Bus'). The two sections operate completely independently.

The control section is used to allow the CPU access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bit and 16-bit (later 32-bit) architectures.

Control Bus lines

The Control Bus contains the following signals:

  • Control Lines (C 0:15) - used to transfer control data
  • Control Lines Parity (CPA)
  • Drive Select (DS 0:2) - selects the entity
  • Register Select (RS 0:4)
  • Controller to Drive (CTOD) - direction of transfer
  • Demand (DEM) - set by the controller to initiate a transfer
  • Transfer (TRA) - acknowledgement from the entity
  • Attention (ATTN) - set by an entity to notify the controller
  • Initialize (INIT) - set by the controller
  • Power Fail (FAIL) - set by the controller to indicate power loss

The first two are bi-directional; all the others are from controller to entity, except for TRA and ATTN.

Data Bus lines

The Data Bus contains the following signals:

  • Data Lines (D 0:17) - used to transfer data
  • Data Lines Parity (DPA)
  • Sync Clock (SCLK) - on write, a request from the entity for data to be sent; on read, notification from the entity that data is ready
  • Write Clock (WCLK) - on write, notification from the controller that data is ready
  • Run (RUN) - a signal from the controller to start a transfer
  • End of Block (EBL) - a signal from the entity to indicate the end of a transfer
  • Exception (EXC) - a signal from the entity to indicate that an error has occurred during a transfer
  • Occupied (OCC) - set by an entity to indicate that it is using the Data Bus

The first two and EXC are bi-directional; all the others are from entity to controller, except for WCLK and RUN.

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