Difference between revisions of "MX15-B Memory Multiplexer"
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* [http://bitsavers.org/pdf/dec/pdp15/hardware/DEC-15-H2XB-D_MX15_EngrDrws_Sep71.pdf MX15 Memory Bus Multiplexer Maintenance Manual Volume 2 - Engineering Drawings] (DEC-15-H2XB-D) | * [http://bitsavers.org/pdf/dec/pdp15/hardware/DEC-15-H2XB-D_MX15_EngrDrws_Sep71.pdf MX15 Memory Bus Multiplexer Maintenance Manual Volume 2 - Engineering Drawings] (DEC-15-H2XB-D) | ||
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Revision as of 14:47, 28 November 2022
The MX15-B Memory Bus Multiplexer was part of the UNICHANNEL 15 System, which allowed a PDP-11 (usually a PDP-11/05) to act as a front end for a PDP-15.
The MX15-B allowed the PDP-11 (both the CPU, and DMA devices on the PDP-11's UNIBUS) access to the PDP-15's main memory, and also allowed the PDP-15 access to the PDP-11's memory - i.e. tuned both memories into shared memory.
Some DMA devices on the UNIBUS (such as the RK11-E) were able to do 18-bit transfers over it; they used the two UNIBUS parity lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 or its memory, but went straight through the MX15-B, directly to the PDP-15's memory.
The MX15-B included an arbiter, so that when the PDP-15 and PDP-11 (both of which are asynchronous) tried to interact with memory at the same time, a choice was made; the PDP-15 was given priority.
Memory addresses in the PDP-11 (which uses byte addressing) were converted to PDP-15 word addressing by dropping the low bit, and conversely for transfers in the other direction. It also converted DATIP and DATOB type UNIBUS cycles (which have no exact equivalents in the PDP-15's memory system) to PDP-15 memory operations with the same effect.
