Difference between revisions of "Motorola MC68030"
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| data bus = 32-bit | | data bus = 32-bit | ||
| year introduced = 1987 | | year introduced = 1987 | ||
| − | | cache = 256 byte icache | + | | cache = 256 byte icache, 256 byte dcache |
| registers = 15 general 32-bit registers (8 data, 7 address) | | registers = 15 general 32-bit registers (8 data, 7 address) | ||
| clock speed = 16, 20, 25, 33, 40, 50 MHz | | clock speed = 16, 20, 25, 33, 40, 50 MHz | ||
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The '''Motorola MC68030''' is a 32-[[bit]] [[microprocessor]] in the [[Motorola M68000 Family]], the successor to the [[Motorola MC68020|68020]]. Later members include the [[Motorola MC68040|68040]] and [[Motorola MC68060|68060]]. | The '''Motorola MC68030''' is a 32-[[bit]] [[microprocessor]] in the [[Motorola M68000 Family]], the successor to the [[Motorola MC68020|68020]]. Later members include the [[Motorola MC68040|68040]] and [[Motorola MC68060|68060]]. | ||
| − | The internal [[architecture]] was similar to the 68020; performance was increased in part by the increased use of [[cache|caching]]; the MC68030 included an additional separate 256-byte cache for data. | + | The internal [[architecture]] was similar to the 68020; performance was increased in part by the increased use of [[cache|caching]]; the MC68030 included an additional separate 256-byte cache for data. The MC68030 Data sheet gives a detailed description of the organization of its caches, and pipe-lining. [http://www.bitsavers.org/components/motorola/68000/MC68030_Data_Sheet_1991.pdf MC68030 Data sheet] |
It was the first family member to include [[memory management]] on the main chip. It did not include [[floating point]]; a separate floating point chip had to be used if [[hardware]] floating point was desired. | It was the first family member to include [[memory management]] on the main chip. It did not include [[floating point]]; a separate floating point chip had to be used if [[hardware]] floating point was desired. | ||
It was used in a number of [[Macintosh]], [[Amiga]] and later [[Atari]] [[personal computer]]s, and also [[workstation]]s from [[NeXT Computer, Inc|NeXT]]. | It was used in a number of [[Macintosh]], [[Amiga]] and later [[Atari]] [[personal computer]]s, and also [[workstation]]s from [[NeXT Computer, Inc|NeXT]]. | ||
| + | |||
| + | The prototyping of this processor, occurring before modern silicon libraries were designed, was debugged in TTL Logic. [https://retrocomputingforum.com/t/68030-prototype-at-1-mhz-18-boards-of-ttl/1387 MC68030 1Mhz Prototype] | ||
| − | Downgraded versions which omitted the [[memory management]] were produced. | + | Downgraded versions which omitted the [[memory management]] were produced for embedded systems. |
{{semi-stub}} | {{semi-stub}} | ||
[[Category: Motorola Microprocessors]] | [[Category: Motorola Microprocessors]] | ||
Revision as of 01:57, 3 March 2022
| MC68030 | |
| Family: | Motorola M68000 Family |
|---|---|
| Architecture: | 32-bit |
| Manufacturer: | Motorola |
| Year Introduced: | 1987 |
| Address bus: | 32-bit |
| Data bus: | 32-bit |
| Number of registers: | 15 general 32-bit registers (8 data, 7 address) |
| Cache: | 256 byte icache, 256 byte dcache |
| Clock Speed: | 16, 20, 25, 33, 40, 50 MHz |
The Motorola MC68030 is a 32-bit microprocessor in the Motorola M68000 Family, the successor to the 68020. Later members include the 68040 and 68060.
The internal architecture was similar to the 68020; performance was increased in part by the increased use of caching; the MC68030 included an additional separate 256-byte cache for data. The MC68030 Data sheet gives a detailed description of the organization of its caches, and pipe-lining. MC68030 Data sheet
It was the first family member to include memory management on the main chip. It did not include floating point; a separate floating point chip had to be used if hardware floating point was desired.
It was used in a number of Macintosh, Amiga and later Atari personal computers, and also workstations from NeXT.
The prototyping of this processor, occurring before modern silicon libraries were designed, was debugged in TTL Logic. MC68030 1Mhz Prototype
Downgraded versions which omitted the memory management were produced for embedded systems.
