PDP-9

PDP-9
Manufacturer:	Digital Equipment Corporation
Year First Shipped:	1966
Form Factor:	minicomputer
Word Size:	18 bits
Logic Type:	PNP Transistor FLIP CHIPs
Design Type:	microcoded
Memory Speed:	1 μsec (9) or 1.5 μsec (9/L)
Physical Address Size:	15 bits (32K words)
Virtual Address Size:	13 bits (direct), 15 bits (extended)
Memory Management:	bounds register
Predecessor(s):	PDP-7
Successor(s):	PDP-15
Price:	US$30K (8KW system)

PDP-9 at MIT Cognitive Information Processing Group.

The PDP-9 was DEC's fourth 18-bit computer, and the first DEC CPU to use microcode. A little over 400 were built. It was a re-implementation of the PDP-7; the PDP-9 'Basic Software System' manual indicates that most PDP-7 software will run, un-modified.

Its principal intended use was for real-time systems, including data recording and process control. A variety of models were offered; the basic system provided 8K words of main memory, and the PDP-9/L was a cost-reduced system with cheaper peripherals and 4KW of memory.

It was a load-store architecture, with a single accumulator. Instructions had a 4-bit opcode, 1 bit of indirect, and 13 bits of address. Opcodes 000-060 were memory-reference instructions; for non-memory operations ('074' opcode), and I/O ('070'), bits in the 'address' field were used to specify details. '064' opcodes were for the optional EAE.

For the high-speed ROM needed for a microcoded design, it used hard-wired core memory, similar to that in the Apollo Guidance Computer. Microinstructions were 36 bits wide, of which 6 were the 'control memory address', the address of the next one; there was no micro-PC. Conditional micro-branching was available by modifying the CMA during that microinstruction. Some front panel functions (START, EXAMINE/DEPOSIT (NEXT), and READ IN) are implemented with microcode. According to a comment in the PDP-11 FAQ from Bernd Ullman, "the first intention was to build a horizontally programmed machine but this was dropped because of the resulting word length needed for the control-words. So some(most ?) of the control signals were encoded and this led to a typical diagonally microprogrammed machine I think."

Multiply/divide was a hardware option, the KE09A EAE, which also performed shifting; it was installed in pre-wired slots in the CPU's backplane. Use of more than 8KW of main memory (all core in the PDP-9) required the Memory Extension Control, KG09A, which provided bank switching. A memory management option, the KX09A, was also available; it included a register to set the boundary between protected and un-protected memory, and two modes for the CPU.

The KF09A Automatic Priority Interrupt option provided 8 levels of interrupt priority, each of which could support up to 8 devices. Each device could provide its own interrupt vector. The DM09 Direct Memory Access Channel Multiplexor Adapter provided high-speed devices with direct access to main memory for data transfers.

A large range of peripherals were available, including DECtape (via the TC02 controller), magnetic tape (via the TC59), drum (RM09 controller) and fixed-head disk (RB09; and RS09, via the RF09 controller). The RM09 and RB09 use the DM09.

See also

• PDP-9 control memory

External links

• PDP-9 - Has manuals for KE09, KG09, KX09, KF09, etc
  • PDP-9 User Handbook
  • TC02 DECtape Transport Control Instruction Manual
  • TC02 DECtape Control Maintenance Manual
• Dartmouth PDP-9 Mini Time-Sharing System
• DEC PDP-9 Restoration - the start of a long saga - 2012-17
  • PDP-9 Restoration Blog Starting 2019
  • PDP-9 Restoration Blog Starting 2020
  • PDP-9 Restoration Blog Starting 2021
  • PDP-9 Restoration Blog 2022
  • PDP-9 Restoration Blog 2023