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- ...''MM11-F core memories''' were [[UNIBUS]] [[main memory]] units; the first UNIBUS memories produced by [[Digital Equipment Corporation|DEC]]. They came out w * 4 x G226 Decoder and Switch4 KB (667 words) - 19:53, 30 July 2023
- ...es) could not be shared (other than via [[software]], or use of a [[UNIBUS switch]]). [[Category: UNIBUS PDP-11s]]2 KB (257 words) - 22:57, 21 August 2021
- | controller = [[RC11 disk controller|RC11]] ([[UNIBUS]]) head switch =2 KB (258 words) - 22:12, 14 August 2023
- | controller = [[RH11 MASSBUS controller|RH11]] ([[UNIBUS]]), [[RH70 MASSBUS controller|RH70]], [[RH10 MASSBUS controller|RH10]] head switch =3 KB (488 words) - 18:37, 14 August 2023
- [[Image:CH11-board.png|thumb|right|250px|CH11 Unibus board]] ...name) and '''QBCHNI''' are [[Chaosnet]] [[network interface]]s, for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are identical5 KB (709 words) - 18:28, 17 September 2023
- ...]s; the 'Bus' light indicates that a [[peripheral]] is in control of the [[UNIBUS]], either for an [[interrupt]], or performing [[Direct Memory Access|DMA]]. The '[[Switch Register]]' is used to enter both addresses and data.2 KB (386 words) - 01:41, 6 July 2023
- ...rial line|synchronous]] and [[asynchronous serial line]]s connected to a [[UNIBUS]] [[device controller]] to be connected to [[modem]]s. It could be set to [ ...kplane]] like the -BB, the -BA plugs into a standard [[UNIBUS]] [[Modified UNIBUS Device|MUD]] slot. It is [[program compatible]] with the DM11-BB (although2 KB (268 words) - 02:40, 16 February 2023
- [[Image:NI1010A.jpg|350px|right|thumb|NI1010A UNIBUS interface]] ...10A''' and '''NI2010A''' are [[Ethernet]] [[network interface]]s for the [[UNIBUS]] and [[QBUS]] respectively. (The two [[device controller]]s are very simil6 KB (797 words) - 21:11, 17 August 2022
- The '''DJ11 Asynchronous 16-Line Multiplexer''' is a [[UNIBUS]] [[peripheral]] which provides up to 16 [[asynchronous serial line]]s. Bot could only be set with a pair of [[DIP switch]]es. A group of [[jumper]]s allowed configuration of separate input and out5 KB (694 words) - 11:36, 18 February 2023
- ...ronous serial line interface''' is the second [[QBUS]] equivalent to the [[UNIBUS]] [[DH11 asynchronous serial line interface|DH11]] (it is a replacement for It can be set (via a switch) to exactly emulate either a DHV11 or [[DHU11 asynchronous serial line inte2 KB (383 words) - 11:47, 17 February 2023
- ...a 8 Kbyte [[core memory|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-B was composed of two [[DEC card form factor|hex]] b ...11-B did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot b3 KB (462 words) - 00:45, 30 July 2023
- ...a 16 Kbyte [[core memory|core]] [[main memory]] for the early [[PDP-11]] [[UNIBUS]] machines. An MM11-C was composed of two [[DEC card form factor|hex]] b ...11-C did not use a custom backplane; it plugged into a standard [[Modified UNIBUS Device|MUD slot]]. The pair was 'thick' enough that a normal board cannot b2 KB (414 words) - 00:46, 30 July 2023
- The '''KW11-W Watchdog Timer''' is a [[UNIBUS]] [[peripheral]] which monitors correct operation of a system; unless it is |Switch Relay Register || WDSRR || 7724062 KB (266 words) - 23:07, 5 November 2022
- '''UNIBUS Device Address''' table; ranges given are inclusive, i.e. a block listed as ...a "17" prepended. A few QBUS [[device controller|devices]] do not exist in UNIBUS form, and are listed in their own right: such cases can be detected by the7 KB (927 words) - 11:26, 12 November 2021
- ...itch does a variety of things, depending on the position the 'Enable/Halt' switch is in. In the Enable position, the CPU continues operating; in the Halt pos [[Category: UNIBUS PDP-11s]]2 KB (372 words) - 18:05, 25 January 2022
- ...console to request that the CPU [[halt]]; this is done with the standard [[UNIBUS]] [[signal]], SACK, and a pair of additional signals, Halt Request and Gran ...[[grant continuity card]]), the machine will irretrievably 'freeze'; see [[UNIBUS and QBUS termination#SACK turnaround and CPU hangs|SACK turnaround and CPU4 KB (650 words) - 16:50, 4 December 2022
- | [[UNIBUS]] Request Logic [[#ref_12|[12]]][[#ref_14|[14]]] | CI-2 Switch Chip [[#ref_23|[23]]]36 KB (3,420 words) - 05:36, 5 November 2022
- ...roller''' is an optional accessory for mid-period [[main memory]] on the [[UNIBUS]]; it provides byte [[parity]] for memory units (such as the [[MM11-D core ...wiring for parity and non-parity memory, no hardware changes are needed to switch from non-parity to parity memory with the M7850. When the M7850 is inserted3 KB (434 words) - 00:07, 20 April 2024
- [[Image:UA11UnibusAnalyzer.jpg|250px|thumb|right|UA11 Unibus Analyzer]] ...ted by a member of the vintage computer community to help with debugging [[UNIBUS]] problems.1 KB (174 words) - 15:31, 9 April 2022
- 6.4 DW750 - Second Unibus The implementation of the SID switch reverses the bit positions of101 KB (10,182 words) - 14:04, 2 July 2022
- potential system hang with high unibus activity, going from standby to local on front panel switch.38 KB (3,857 words) - 14:02, 2 July 2022
- |DW780 | UNIBUS ADAPTOR | 01,C1+| 01,C1 | 01,C1 | 01,C1 | |DW780 | UNIBUS ADAPTOR | 01,C1+| 01,C1 | 01,C1 | |118 KB (7,116 words) - 14:05, 2 July 2022
- 5.7 DW780 - Unibus Adapter 5.7 DW780 11780 UNIBUS ADAPTER70 KB (7,782 words) - 14:04, 2 July 2022
- * [[Digital Ethernet UNIBUS Network Adapter|DEUNA]] Ethernet Controller To avoid having to reboot, we switch to Single User Mode now - returning to Multiuser Mode will activate the new73 KB (9,059 words) - 20:56, 22 May 2023
- ...single-line [[synchronous serial line]] [[peripheral|interface]] for the [[UNIBUS]]. It uses [[Direct Memory Access|DMA]] to transfer data to and from [[main ...03), which can be configured to one of 4 choices via [[jumper]]s and [[DIP switch]]es, one of:2 KB (315 words) - 23:54, 13 May 2023
- ...multi-point [[synchronous serial line]] [[peripheral|interface]] for the [[UNIBUS]]. It uses [[Direct Memory Access|DMA]] to transfer data to and from [[main ...03), which can be configured to one of 4 choices via [[jumper]]s and [[DIP switch]]es, one of:2 KB (277 words) - 00:21, 14 May 2023
- === Switch to Multi-User Mode === rh11 pdp11 unibus RM02, RP04/5/6, ML11, RS03/433 KB (4,919 words) - 12:31, 21 June 2023
- ...itch does a variety of things, depending on the position the 'Enable/Halt' switch is in. In the Enable position, the CPU continues operating; in the Halt pos [[Category: UNIBUS PDP-11s]]2 KB (397 words) - 20:32, 30 June 2023
- ...ted. Configuration is done with a combination of [[jumper]]s and two [[DIP switch]]es. ...BUS, or through two independent 2KB windows (somewhat like later, larger [[UNIBUS]] ROM cards). The MRV11-A was a [[DEC card form factor|dual]]-height card,1 KB (176 words) - 18:37, 19 July 2023
- [[Image:MITXGP.jpg|thumb|rigt|300px|UNIBUS XGP interface (at the top of its controlling PDP-11, at right) along with t The '''MIT UNIBUS XGP interface''' was a one-off [[UNIBUS]] [[peripheral]] which drove a [[Xerox Graphics Printer]], the earliest [[r5 KB (869 words) - 13:30, 27 February 2024
- *** [[MIT UNIBUS XGP interface|XGP interface]] *** [[UNIBUS Experimental Ethernet interface]]6 KB (863 words) - 15:11, 24 April 2024
- ...ne of the very first [[bit-mapped display]] systems. It consisted of two [[UNIBUS]] [[device]]s, built onto a [[PDP-11/10]] (the 'TV-11'), which was connecte ...ependent [[frame buffer]]s. The outputs from these were run into a [[video switch]], which could drive up to 63 stations (about 30 were actually installed, o3 KB (482 words) - 18:06, 20 March 2024
