Private Memory Interconnect
The Private Memory Interconnect (PMI) bus was a high-performance bus, a variant of the QBUS, introduced with the KDJ11-B CPU. It also provides means for the CPU and a KTJ11-B UNIBUS adapter to communicate in providing UNIBUS service.
For data transfer to main memory, PMI provides two primary modes:
- single- and double-word data reads, and single-word and single-byte writes;
- block mode, which can read up to 16 words.
When operating with a KTJ11-B, it provides means for UNIBUS devices to perform DMA cycles (mapped to the full 22-bit address space via a UNIBUS map), and to interrupt the CPU.
The PMI uses the CD interconnect specified for some QBUS backplanes to carry PMI-specific signals; PMI also uses other existing QBUS signals (e.g. BDAL00-21), on their standard pins. Note that PMI and QBUS devices and memories can co-exist on the same physical bus; for example, in a PDP-11/83 system, the CPU will use PMI to talk to the main memory, but DMA devices on the QBUS will use normal QBUS protocols to talk to that same memory.
Use of the standard CD interconnect means that PMI-based systems (such as the -11/83) can be constructed with a standard Q/CD backplane, a KDJ11-B CPU card, and one or more PMI memories. The PDP-11/84 and PDP-11/94 have a special backplane with a slightly modified form of CD interconnect for its PMI (below).
Contents
CD interconnect details
The use of the CD interconnect is somewhat idiosyncratic, because it is desirable to be able to plug in a variable number of memory cards - i.e. create a true 'bus', by connecting together more than two slots. The nature of the CD interconnect, which groups slots into pairs, would normally make this difficult.
If the CPU card sent out the PMI bus on the bottom (2, or solder-side) pins, then the memory card would have to take the PMI bus in on its top (1, component-side) pins, and repeat the bus through on its bottom pins, for use by a notional 'next memory card'. However, if the next card is not a PMI memory card, this will result in the PMI bus being sent to a card which does not use it - possibly with harmful effects.
So, instead, PMI CPU cards emit the PMI bus on their top CD connector pins, and the memory cards take the bus in on their bottom pins, and repeat it through to their top pins. Thus, PMI memory cards must be placed in a Q/CD backplane above the CPU card.
An exception to this rule is the special backplane in the -11/84 and -11/94, in which the CD connectors of the QBUS section of the backplane are wired to form a true bus; in this machine, the PMI memory cards are placed below the processor card.
Pinout
PMI pins are identified in the standard DEC manner; there are four connectors, A-B; pins on the component side are 1, those on the solder side are 2. Pins are identified by the 'DEC alphabet', A-V, with G, I, O and Q dropped.
The tables below show the pins used for normal PMI master-slave cycles (as in the PDP-11/83), and those used to communicate with the KTJ11-B UNIBUS adapter (-11/84 and -11/94 only).
Master-slave signals
| Pin | Signal | Meaning |
|---|---|---|
| CE1 | PBCYC | Indicates a PMI cycle |
| CR1 | PBSY | PMI busy |
| DC1 | PBYT | Used with BWTBT to indicate type of PMI cycle |
| CP1 | PBLKM | Indicates a PMI block mode transfer (i.e. multi-word) |
| CB1 | PSSEL | Slave select |
| DB1 | PWTSTB | Write strobe |
| CJ1 | PSBFUL | Slave buffer full |
| CM1 | PRDSTB | Read strobe |
| CH1 | PHBPAR | High byte parity |
| CK1 | PLBPAR | Low byte parity |
In PMI memory cards such as the MSV11-R, these signals are all connected to the solder-side (2) pins, as well as the component-side (1) pins.
UNIBUS adapter communication signals
| Pin | Signal | Meaning |
|---|---|---|
| CF1 | PUBSYS | UNIBUS adapter present |
| DD1 | PMAPE | Enable UNIBUS map for UNIBUS->PMI |
| CD1 | PUBMEM | CPU access to UNIBUS |
| CV1 | PUBTMO | UNIBUS timeout |
Some PMI memory cards read the PUBMEM signal.
