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- | image = PDP11-45.jpg | caption = A PDP-11/456 KB (895 words) - 23:52, 29 February 2024
- ...took the high-performance [[Central Processing Unit|CPU]] of the [[PDP-11/45]] (implemented in [[SSI]] [[Schottky TTL]] logic), and augmented it with: ...ted to what had been the FastBus high-speed memory interface on the PDP-11/45 CPU5 KB (729 words) - 23:43, 29 February 2024
- ...because of it. While the BSD world stalled during this lawsuit, Linux was able to thrive, and pick up users. *[[Linux 0.02|0.02]] The first 'working' public version, able to run bash & GCC.28 KB (4,805 words) - 18:01, 29 February 2024
- Chapter 22 - Use of the basic graphical interface 45 1: Increase the size of the areas of entry / exit of the "cache" of91 KB (12,020 words) - 17:55, 13 August 2019
- Axik Ace Cache 486DX-33V Axik Ace Cache 486DX-33VG144 KB (18,526 words) - 03:17, 17 December 2018
- EISA X AMIscsi Series 48 (with cache) [28,1] ISA-16 X DPT PM2011b (with cache) [28]279 KB (34,581 words) - 03:21, 17 December 2018
- ...marily invoked directly from the shell. A casual user probably will not be able to distinguish the hardware, except by issuing the command "who am i" (whic ...and for deadstart load, and physically carried these tapes from the PDP-11/45 to the VAX-11/780.49 KB (7,745 words) - 14:29, 6 May 2023
- is now able to boot from the selected harddisk. To complete the NetBSD 5.0.2 (GENERIC) #0: Sat Feb 6 22:45:58 UTC 20108 KB (1,125 words) - 02:02, 18 November 2010
- Cache/Buffer KB Landing Zone Supply voltage 5/12 V Temperature *C 10 45 | -40 6019 KB (2,330 words) - 14:58, 5 January 2024
- 5.2.5 Page Translation Cache 11.2.3 Cache Considerations890 KB (107,817 words) - 03:20, 3 January 2024
- * M9301-YC - [[PDP-11/70]] version; contained basic CPU, cache and memory diagnostics, booted from various devices (TM11, TC11, RK11, RP11 ...9, 481A9, 482A9, 483A9) - All models (auto-start not available on [[PDP-11/45]], [[PDP-11/50]]); had basic diagnostics, console emulator, booted from var9 KB (1,304 words) - 19:41, 7 December 2021
- ...). On machines which have only [[UNIBUS]] memory (e.g. PDP-11/40, [[PDP-11/45]], etc) these registers are 12 bits long, since the maximum amount of physi | Don't Cache || colspan=7 | Length || Trapped || Written || colspan=2 | Unused || Direct9 KB (1,311 words) - 18:10, 2 July 2023
- | Cache = 2KB VIC [[#ref_2|[2]]] | Primary-cache = 8KB physical [[#ref_2|[2]]]1 KB (137 words) - 15:59, 23 May 2023
- | Cache = 64KB [[#ref_1|[1]]] | Console-device = 452 KB (174 words) - 16:57, 23 May 2023
- [[Image:BrochureAbleENABLE.jpg|250px|thumb|right|Able ENABLE, as shown in an Able brochure]] ...ice which allowed the smaller [[PDP-11]]'s ([[PDP-11/34]] through [[PDP-11/45]]) to have up to 4 MBytes of [[main memory]].9 KB (1,569 words) - 15:47, 6 February 2024
- ...[[PDP-11/45]]'s [[KB11-A CPU]]; the -11/70 is basically an -11/45 with a [[cache]], more [[main memory]], and provision for high/speed [[input/output|I/O]] Full [[PDP-11 Memory Management]] and the cache were standard on all KB11-B's. It used a special 32-[[bit]] wide memory [[b3 KB (456 words) - 21:08, 2 July 2023
- [[Image:AbleLogo.jpg|right|thumb|200px|Able's logo]] ...which made a variety of [[device controller]]s and similar devices (e.g. [[cache]]s) for [[PDP-11]]s and other machines which used the [[UNIBUS]] or [[QBUS]4 KB (493 words) - 18:48, 5 December 2022
- ! Item !! 03 !! 23/24 !! 73/83/93 !! 04 !! 05 !! 20 !! 34 !! 40 !! 44 !! 45 !! 70 | Explicit [[cache|caching]] control per-[[segment]] || - || - || @ || - || - || - || || - ||2 KB (343 words) - 03:12, 13 September 2020
- | 772440-76 || TU16/45/77 | 777744 || Memory Error (11/70, /60, /44, /73) Cache Memory Error (11/34 w/ KK11-A)7 KB (927 words) - 11:26, 12 November 2021
- | RIGEL Backup Cache Chip [[#ref_27|[27]]] | Mistral Backup Cache Controller chip (C-chip) [[#ref_29|[29]]]36 KB (3,420 words) - 05:36, 5 November 2022
