Stanford 1822 Interface

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The Stanford 1822 Interface provided an conversion between a parallel port and an 1822 interface; the latter could connect to anything that provided a BBN-1822 bit-serial interface, most commonly including IMP interfaces to ARPANET IMPs, but also Packet Radio Network interfaces.

(The name is made up; examining contemporaneous documentation does not reveal an official or universally-used name. It was also commonly called the SRI 1822 interface, or some variant thereof, since although it was initially created at the Digital Systems Laboratory at Stanford University, SRI shortly thereafter took over provision of boards to other DARPA contractors who wanted them.)

It was for all machines (mostly PDP-11s) with either a UNIBUS (via a DR11-C parallel interface) or QBUS (via a DRV11) (which had identical parallel ports). Since it used the programmed I/O of the underlying DR11-C/DRV11, with an interrupt for every byte, it was not very suitable for high-throughput applications.

It consisted of a dual-width board with three Berg connector headers on it; two held flat cables going to the parallel interface, which connected up to the host computer's input/output bus. A 26-pin Berg header held a cable which led to the standard round Amphenol connector used for the 1822 interface. This board plugged into either the UNIBUS or QBUS backplane, near the parallel interface board.


The device had three control and buffer registers, which could be configured to any three sequential word locations in the I/O page. The first was normally configured to addresses 767770-767774; the second to 767760-767764, the third to 767750-767754, and so on.

Register Abbreviation Address
Control and Status Register SCSR 0167770
Output Buffer Register SOUTBUF 0167772
Input Buffer Register SINBUF 0167774

In the register contents (below), bits which are read/write or unused are shown in normal font, those which are read-only are in italics.

"Reading or writing into a register while it is in the process of transferring a byte may cause some bits to become lost and/or out of synchronization. This can waiting until be avoided by either an interrupt or interrupt request (as seen in the status register) is present before accessing the register."

Status Register (SCSR)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • RDONE - Receive done, interrupt requested
  • TDONE - Transmit done, interrupt requested
  • TINTE - Transmit Interrupt Enable
  • RINTE - Receive Interrupt Enable
  • RENABL - Receive data enable
  • TENABL - Transmit data enable

Output Buffer Register (SOUTBUF)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • HSTCLR - Open Host Ready relay
  • HSTPWR - Close Host Ready relay
  • LSTBYT - Last byte sent

"Either bit 13 OR bit 12 should be set. NOT BOTH."

Input Buffer Register (SINBUF)

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
  • IMPODD - IMP was down or last byte received
  • IMPDWN - "IMP has been down since the last interrupt was serviced"
  • HSTMRY - Host relay check, 0 = closed
  • IMPMRY - IMP relay check, 0 = closed
  • LSTBYT - Last byte received

"The interface will receive bits until either it is full, or it receives the last IMP data bit (LIDB) signal. At this point the interface stops and requests an interrupt. It will not accept any new bits until the present load of bits is read from INBUF. ... Reading the receive register clears the receive buffer making it ready for another byte. Thus program testing of control bits should be done after the contents of the receive register have been moved elsewhere."

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