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  • [[Category: PDP-11 UNIBUS Processors]]
    6 KB (1,045 words) - 22:47, 31 March 2022
  • In addition to several standard [[UNIBUS]] signals (SACK, INIT, DCLO and ACLO), it also used a pair of additional ba [[Category: PDP-11 UNIBUS Processors]]
    2 KB (358 words) - 18:29, 3 April 2022
  • ...d the [[VAX Bus Interconnect|VAXBI]] [[bus]]; it can support an optional [[UNIBUS]] adapter. ...-20 of the PDF) and covered in detail in Chapter 5, "VAX 8200 and VAX 8300 Processors" (pp. 86-102 of the PDF)
    2 KB (208 words) - 23:08, 28 March 2024
  • ...d the [[VAX Bus Interconnect|VAXBI]] [[bus]]; it can support an optional [[UNIBUS]] adapter. ...-20 of the PDF) and covered in detail in Chapter 5, "VAX 8200 and VAX 8300 Processors" (pp. 86-102 of the PDF)
    2 KB (210 words) - 23:10, 28 March 2024
  • The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture ...Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] adapters (which are used to perform all [[input/output|I/O]] in the syste
    8 KB (1,237 words) - 19:48, 14 July 2023
  • [[Category: PDP-11 UNIBUS Processors]]
    4 KB (734 words) - 02:17, 13 October 2022
  • ...ing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 [[parity]] bits (one for the tag); and two valid b [[Category: PDP-11 UNIBUS Processors]]
    4 KB (553 words) - 02:36, 12 October 2022
  • ...US [[Small Peripheral Controller|SPC]] slot; that slot also contained the 'UNIBUS out'. | 9 || colspan="2" style="text-align:center;" | UNIBUS Out || colspan="4" style="text-align:center;" | SPC
    4 KB (588 words) - 05:52, 8 April 2024
  • ...also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connect ...DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.
    5 KB (664 words) - 17:27, 7 November 2023
  • ...[graphics terminal]]s, and provide [[Chaosnet]] [[front end]]s to [[KL10]] processors. * [[UNIBUS Experimental Ethernet interface|3 Mbit Ethernet]] interface
    3 KB (347 words) - 08:50, 27 February 2024
  • ...as a bus arbitrator, so that the machine can be a 'slave' processor, on a UNIBUS controlled by another CPU. [[Category: PDP-11 UNIBUS Processors]]
    11 KB (1,726 words) - 21:07, 2 July 2023
  • In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use the special high-speed [[MS11 Semiconductor Me * M8104 Processor Data and UNIBUS Registers
    3 KB (395 words) - 21:08, 2 July 2023
  • In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use the special high-speed [[MS11 Semiconductor Me * M8104 Processor Data and UNIBUS Registers
    2 KB (307 words) - 12:32, 11 October 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    2 KB (231 words) - 02:38, 12 October 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    2 KB (304 words) - 02:33, 12 October 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    961 bytes (149 words) - 02:20, 13 October 2022
  • ...t|chips]], and not a [[microprocessor]], and also nearly the last native [[UNIBUS]] CPU (except for the [[KDF11-U CPU|KDF11-U]]). ...ess to the memory via a [[UNIBUS map]] which connected the two, and mapped UNIBUS addresses to main memory addresses.
    4 KB (668 words) - 15:59, 6 February 2024
  • ...o the memory via a [[UNIBUS map]] which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to * M8134 Processor Data and UNIBUS Registers
    3 KB (456 words) - 21:08, 2 July 2023
  • [[Category: PDP-11 UNIBUS Processors]]
    2 KB (260 words) - 21:03, 24 October 2022
  • ...ipheral|devices]] such as the [[RP11 disk controller]]). It carries all 56 UNIBUS [[signal]]s, and 64 [[ground]] lines (alternating with the signals, to prev ...t board|PCB]] ([[M919]] and [[M929]]), which plug into the 'UNIBUS in' or 'UNIBUS out' slot of the element's [[backplane]].
    1 KB (176 words) - 12:47, 16 October 2021

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