Search results

From Computer History Wiki
Jump to: navigation, search
  • 1 KB (166 words) - 00:32, 23 June 2020
  • ...-B Floating-Point Processor]] and [[KT11-C Memory Management Unit]] of the PDP-11/45 plugged into the CPU's [[backplane]]. ...e special high-speed [[MS11 Semiconductor Memory System]], specific to the PDP-11/45, which plugged into a special [[bus]], the Fastbus, which was also part
    3 KB (395 words) - 21:08, 2 July 2023
  • ...ocessing Unit|CPU]] is the later [[Central Processing Unit|CPU]] for the [[PDP-11/45]]; it differed from the earlier [[KB11-A CPU]] in that is used the [[syn ...e special high-speed [[MS11 Semiconductor Memory System]], specific to the PDP-11/45, which plugged into a special [[bus]], the Fastbus, which was also part
    2 KB (307 words) - 12:32, 11 October 2022
  • ...Memory Management]] architecture; in fact, the KT11-C is the archetype for PDP-11 memory management units. [[Category: PDP-11 UNIBUS Processors]]
    2 KB (231 words) - 02:38, 12 October 2022
  • ...tional [[PDP-11 Extended Instruction Set]] for the [[KD11-A CPU]] of the [[PDP-11/40]]; it implements multiply, divide, and multi-bit shift instructions. It [[Category: PDP-11 UNIBUS Processors]]
    2 KB (304 words) - 02:33, 12 October 2022
  • ...the [[hardware]] [[floating point]] option for the [[KD11-Z CPU]] of the [[PDP-11/44]]. It implements the full [[FP11 floating point]]; it consists of a sing [[Category: PDP-11 UNIBUS Processors]]
    961 bytes (149 words) - 02:20, 13 October 2022
  • ...the terminal letter code 'Z' was a tip to the fact that it was the last [[PDP-11]] CPU to be made out of discrete [[integrated circuit|chips]], and not a [[ Full [[PDP-11 Memory Management]] and a [[cache]] (the [[KK11-B Cache Memory|KK11-B]]) we
    4 KB (668 words) - 15:59, 6 February 2024
  • ...U]] is the earlier CPU for the [[PDP-11/70]]. It is heavily based on the [[PDP-11/45]]'s [[KB11-A CPU]]; the -11/70 is basically an -11/45 with a [[cache]], Full [[PDP-11 Memory Management]] and the cache were standard on all KB11-B's. It used a
    3 KB (456 words) - 21:08, 2 July 2023
  • The '''KB11-C''' [[Central Processing Unit|CPU]] is the later CPU for the [[PDP-11/70]]; it is basically the same as the earlier [[KB11-B CPU]], except that i '''''Note''''': ''The DEC documentation contains an error here. The "PDP-11/70 Maintenance and Installation Manual", EK-11070-MM-002, refers to the M81
    2 KB (260 words) - 21:03, 24 October 2022
  • ...oating point]] units of many [[PDP-11]]s); [[channel]]s are effectively co-processors which are specialized to doing [[input/output|I/O]].
    528 bytes (79 words) - 16:25, 15 December 2018
  • ...ircuit board|boards]] which use the [[F-11 chip set]]; it implements the [[PDP-11 Commercial Instruction Set]]. [[Category: PDP-11 Processors]]
    650 bytes (102 words) - 18:57, 30 May 2021
  • [[Category: PDP-11 Processors]]
    2 KB (383 words) - 02:31, 12 October 2022
  • ...[[PDP-11]]s. (No [[PDP-8 family|PDP-8]] or other [[List of Programmed Data Processors|early DEC system]] [[device controller]] has yet been seen for it, although
    2 KB (258 words) - 22:12, 14 August 2023
  • ...it|chip]] for [[LSI-11 chip set]] which adds support for a subset of the [[PDP-11 Commercial Instruction Set]], sometimes known as DIS ([[DIBOL]] instruction It also apparently includes the [[PDP-11 Extended Instruction Set]] (but not the [[FIS floating point|FIS]]).
    1 KB (241 words) - 21:11, 2 July 2023
  • ...grated circuit|chip]] for [[LSI-11 chip set]] which adds support for the [[PDP-11 Extended Instruction Set]], but not also [[FIS floating point]] (like the [ [[Category: PDP-11 Processors]]
    466 bytes (75 words) - 21:12, 2 July 2023
  • ...n any of the three uROM positions. The first two uROMs contain the basic [[PDP-11]] [[instruction set]]; the third uROM is optional, and a number of differen ...Commercial Instruction Set‎|KEV11-C]] provides a subset of the PDP-11 [[PDP-11 Commercial Instruction Set|CIS]] (it also apparently includes the EIS, but
    5 KB (773 words) - 22:42, 20 December 2023
  • ...rd form factor|hex]] [[printed circuit board|card]] (the M7263), the first PDP-11 CPU to be built on a single card. ...ction Set|EIS]] [[instruction]]s, or the various instructions added to the PDP-11 [[instruction set]] (XOR, SOB, SXT and MARK).
    2 KB (385 words) - 22:37, 31 March 2022
  • ...1/40]] which provided [[memory management]]. It did not provide the full [[PDP-11 Memory Management]], but the simplified subset; in fact, the KT11-D is the ...ee e.g. EK-11040-TM-002, pg. 4-22) but this may just be an artifact of DEC PDP-11 software.
    2 KB (258 words) - 00:29, 30 December 2023
  • ...]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used a [[UNIBUS]] for its [[main memory]] access ( * [http://www.bitsavers.org/pdf/dec/pdp11/1160/ PDP-11/60] - BitSavers
    4 KB (536 words) - 12:34, 11 October 2022
  • ...ional [[hardware]] [[floating point]] unit for the [[KD11-K CPU]] of the [[PDP-11/60]]. The KD11-K provided the full [[FP11 floating point]] using [[microcod [[Category: PDP-11 UNIBUS Processors]]
    1 KB (229 words) - 02:19, 13 October 2022
  • ...via what was effectively a [[local area network|LAN]] which ran to all the processors. That LAN was to be a [[bus]] (similar to an [[Ethernet]]) in the initial i
    3 KB (478 words) - 20:31, 1 March 2024
  • ...CPUs''' were [[Digital Equipment Corporation|DEC]]'s first cost-reduced [[PDP-11]] [[Central Processing Unit|CPUs]], using a [[microprocessor]] (the [[LSI-1 ...cycle]]s, at 1.4-2.1 μseconds per cycle - depending on the operand modes, PDP-11 instructions could add up to 6 additional memory cycles per instruction, ab
    3 KB (453 words) - 16:35, 6 April 2024
  • ...arbitration works on these two buses. For those details, refer to DEC's ''PDP-11 Bus Handbook''. [1] It covers both the Unibus and QBUS and we will refer to ...nd occasionally had editing errors. Another take on the Unibus is found in PDP-11 ''Unibus Design Description'' [2] and a later description of the QBUS (whic
    21 KB (3,685 words) - 04:35, 28 November 2023
  • [[Category: PDP-10 Processors]]
    569 bytes (87 words) - 13:13, 16 November 2023
  • ...for the [[KD11-A CPU]] of the [[PDP-11/40]]. The basic KD11-A implements [[PDP-11 stacks#Stack limits|stack limit]] functionality, but at a fixed [[address]] ...avers.org/pdf/dec/pdp11/1140/PDP-1140_System_Engr_Drawings_Rev_P_Jun74.pdf PDP-11/40 system engineering drawings] (pp. 109-113 of the PDF)
    995 bytes (154 words) - 02:35, 12 October 2022
  • ...ocumentation used 'T-11') was a [[microprocessor]] implementation of the [[PDP-11 architecture]]. It was primarily intended for use in [[embedded system]]s, The T-11 implemented a subset of the PDP-11 architecture; it had neither [[memory management]], nor [[floating point]],
    2 KB (283 words) - 02:27, 20 September 2022
  • ...n of Two Microprogrammable Processors] - overview of the MLP-900 and the [[PDP-11/40E]]
    3 KB (477 words) - 15:39, 24 April 2024
  • ...d, as well as a subset of the [[SDS 940|940]] instruction set. Two of the processors have expanded hardware capabilities and run user code. The other four are ...nters. This was replaced by a [[Hewlett-Packard|HP]]2100A at Hawaii. A [[PDP-11/10]] running [[ELF operating system|ELF]] connected to the [[ARPANET]].
    2 KB (319 words) - 17:44, 29 April 2024
  • ...'KK11-B Cache Memory''' was a standard part of the [[KD11-Z CPU]] of the [[PDP-11/44]], a high-speed [[cache]] for the [[Central Processing Unit|CPU]]. ...ostly at the same locations as some of the memory/cache registers in the [[PDP-11/70]], but they are generally incompatible with those in the /70.
    3 KB (501 words) - 16:27, 6 February 2024
  • ...the [[KD11-E CPU]] of the [[PDP-11/34]], and the [[KD11-EA CPU]] of the [[PDP-11/34A]]. ...E%20KD11-D%20Processor%20Manual%20(PDP-11-04).pdf KD11-D Processor Manual (PDP-11/04)] (EK-KD11D-TM-PRE)
    4 KB (650 words) - 16:50, 4 December 2022
  • The '''PDP-11/40E''' was a modified version of the basic [[PDP-11/40]], produced in small numbers at [[CMU]] for use in the [[C.mmp]] [[multi The PDP-11/40E was also used at [[BBN]] for [[INTERLISP|Interlisp-11]].
    1 KB (183 words) - 16:20, 11 January 2024
  • ...called [[S-box]] format, for the [[BA200]] enclosure. It was used in the [[PDP-11/53]] and the [[DECserver 500]] [[Terminal Server]]. [[Category: PDP-11 QBUS Processors]]
    3 KB (529 words) - 12:01, 15 August 2022
  • ...or the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] of the [[PDP-11/34]]. ...[M9302 UNIBUS terminator|M9302]]], the SACK timeout feature found on other processors is not required"
    4 KB (740 words) - 16:41, 20 April 2022
  • The KD32 uses standard Q22 [[QBUS memories]] (as used in QBUS [[PDP-11]]s). [[Category: VAX QBUS Processors]]
    2 KB (298 words) - 06:29, 28 June 2022
  • ...t]] for the [[PDP-11/20]]. (Starting with the next [[PDP-11]] model, the [[PDP-11/45]], memory management was standard, so the KS11 became obsolete.) It was [[Category: PDP-11 UNIBUS Processors]]
    5 KB (754 words) - 17:58, 29 February 2024
  • ...tion models introduced [[Symmetric Multiprocessing]] (SMP) with up to four processors in conjunction with [[VMS]] V5.0. ...e operations; the first generation models used a special version of the [[PDP-11]]-based [[Professional 300 Series|Professional 380]], the second generation
    6 KB (844 words) - 22:15, 29 April 2024
  • ...ctionality [[graphics]] control module capable of working on the following processors: * [[PDP-11/23+]]
    3 KB (368 words) - 19:42, 9 March 2024
  • Micro/pdp-11 optional software load/unload Micro/pdp-11 optional software load/unload
    33 KB (4,919 words) - 12:31, 21 June 2023
  • ...s and Services for new processors while Software Products and Services for processors already introduced remained in the old 7-Character Format. *J - [[PDP-11]] [[UNIBUS]]-based ([[RT-11]], [[ULTRIX-11]])
    6 KB (972 words) - 17:56, 25 April 2024
  • ...ssor]] for the [[KD11-Z CPU]] of the [[PDP-11/44]] which implemented the [[PDP-11 Commercial Instruction Set]]. [[Category: PDP-11 UNIBUS Processors]]
    831 bytes (119 words) - 21:09, 5 July 2023
  • ...] version of the [[PDP-11/20]]. It was essentially the [[KA11 CPU]] of the PDP-11/20, with several minor emendations to justify a lower price: The 'basic' [[front panel]] of the PDP-11/15 was the KY11-B; it had only 'power' and 'run' lights, and 'start', 'halt
    1 KB (202 words) - 01:40, 6 July 2023
  • [[Category: DEC Processors]]
    11 KB (1,387 words) - 09:37, 13 August 2023
  • ...stem''' is based on the [[VSV11 Graphic System]] enhanced by a dedicated [[PDP-11]] processor and a special high level Picture Definition Language. The full An intelligent, multiple display control system for PDP-11 and [[VAX]] computers.
    16 KB (2,398 words) - 12:26, 27 February 2024
  • CI20 has started, a CFRECN BUGHLT is issued on processors with lower
    53 KB (6,770 words) - 13:15, 16 November 2023
  • [[Category: PDP-10 Processors]]
    2 KB (342 words) - 18:10, 14 November 2023
  • [[Category: PDP-10 Processors]]
    3 KB (490 words) - 18:09, 14 November 2023
  • ...ode]] in the CPU; on high-end systems, the channels were discrete physical processors. * [[DX11-B System 360/370 Channel to PDP-11 Unibus Interface]]
    5 KB (704 words) - 17:20, 9 April 2024

View (previous 50 | next 50) (20 | 50 | 100 | 250 | 500)