FIS floating point
Most supported a more capable floating point capability, the FP11 floating point. Even though the instructions were not compatible between the two, the FIS was useful since DEC's FORTRAN compiler (the main 'target' for the FIS) for the PDP-11 used threaded code, and was thus able, via conditional assembly of the run-time support, to easily make use of the low-capability, but low-cost, FIS version.
As with the FP11 version, it was tightly integrated with the CPU, so that the CPU processed a mix of 'regular' and floating point instructions.
FIS-type floating point supported only short (32 bit) floating point numbers; it used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining 23 bits were the fractional part.
It provided only the four basic arithmetic operations. Checking for underflow. overflow, and division by zero was performed in hardware, and would cause an trap if they happened; condition code bits in the main CPU recorded the outcome of operations.
The instructions used one of the regular PDP-11 registers as a pointer to load and store floating point data from/to memory; floating point values could only be stored in main memory, generally on the stack; there was no way to store floating point values in the CPU.
The initial implementation was the optional KE11-F Floating Instruction Set for the KD11-A CPU for the PDP-11/40; it was later used in the optional KEV11-A floating point option for the LSI-11 CPU of the PDP-11/03.
- Ronald F. Brender, Turning Cousins into Sisters: An Example of Software Smoothing of Hardware Differences, in C. Gordon Bell, J. Craig Mudge, John. E. McNamara, Computer Engineering: A DEC View of Hardware Systems Design, Digital Press, Bedford, 1978 - Explains how DEC software made use of the FIS instructions