FIS floating point

From Computer History Wiki
Jump to: navigation, search

FIS (Floating Instruction Set) floating point is the term used for the floating point instructions supported by a few PDP-11s which had hardware support for floating point. (Most supported a more capable floating point capability, the FP11 floating point.) It was tightly integrated with the CPU, so that the CPU processed a mix of 'regular' and floating point instructions.

Architecture

FIS-type floating point supported only short (32 bit) floating point numbers; it used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining 23 bits were the fractional part.

It provided only the four basic arithmetic operations. Checking for underflow. overflow, and division by zero was performed in hardware, and would cause an trap if they happened; condition code bits in the main CPU recorded the outcome of operations.

The instructions used one of the regular PDP-11 registers as a pointer to load and store floating point data from/to memory; floating point values could only be stored in main memory, generally on the stack; there was no way to store floating point values in the CPU.

Implementations

The initial implementation was the optional KE11-F Floating Instruction Set for the KD11-A CPU for the PDP-11/40; it was later used in the optional KEV11-A floating point option for the LSI-11 CPU of the PDP-11/03.