LSI-11

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The LSI-11 was DEC's first cost-reduced PDP-11 processor, using the QBUS. Several different LSI-11 models exist, including the KDF11-F (quad form factor, M7264, in numerous variants), and the KD11-HA (dual form factor, M7270), also called the LSI-11/2.

They were the first PDP-11 model to not have a front panel to control them; instead, as a cost-reduction measure, when the CPU is halted, specialized microcode used the main serial line as a operating console. The command set is named Octal Debugging Technique (ODT); there are commands to read and write memory, start the CPU, etc. The main serial interface is normally configured so that when the CPU is running, sending a break on the console serial line halts the CPU.

Implementation

All LSI-11 models use the same chip set internally, the Western Digital WD16/CP1600 (alternative designations). The chip set consists of a data path chip, a control chip, and two or three microcode ROMs (each holding 512 words which are 22 bits wide).

The data path chip contains data paths, registers, and logic to perform micro-instructions; it includes a register file, the ALU, condition flags logic, and a data port which gives access to the QBUS' data/address line. The control chip contains micro-instruction sequencing, and control for the data port; it includes a 'programmable translation array', which decodes macro-instructions to produce microcode addresses, the 'location counter' (micro-program counter), the 'return register' (microcode subroutine return), and interrupt logic.

The uROMs all have the same pinout, and are wired in parallel, so they can be placed in any of the three uROM positions. The first two uROMs contain the basic PDP-11 instruction set; the third uROM is optional, and a number of different choices are available. One is the KEV11-A, for the EIS/FIS instructions; the KEV11-B provides EIS without FIS.

The KEV11-C (see below for uROM information) provides a subset of the PDP-11 CIS, sometimes known as DIS (DIBOL instruction set). It also apparently includes the EIS (but not the FIS). DIS came as a standard in some commercial-oriented LSI-11 systems; the KD11-P and KD11-Q processors (M7264-BB and M7264-YB, respectively) are CPU models with the KEV11-C installed. The DIS cannot be used with the FIS, not only because of the limited number of uROM slots, but also because the DIS and basic instruction set together use the entire uROM address space.

LSI-11

The LSI-11 is a quad board (M7264) with additional functionality on-board (making possible a single-board computer): the base KD11-F version includes 4KW of MOS RAM; the KD11-H version has the RAM deleted; the KD11-Q includes the KEV11-C.

The chip order (from the left, with the contact finger edge down, and the component side facing the viewer) is KEV11, uROM 1, uROM 0, Control, Data Path.

LSI-11/2

The LSI-11 is a dual board (M7270); it contains the processor, and nothing else.

Note: The image in the "Microcomputer Products Handbook" (pg. C-18) is erroneous; the order of the chips (from the handle end) is, in fact, KEV11, Control, uROM 1, uROM 0, Data Path (per the KD11-HA print set); the order given in the Handbook is that for the LSI-11 (no doubt an image was re-used without checking).

Chip variants

There are a number of variants of all the various uROM chips; it is not known if all variants are completely inter-operable (i.e. any revision of any chip can be replaced with any other, and have the machine still work), so combinations will be listed.

Chip numbers of the form 23-xxxxx-rr, etc are DEC part numbers (where 'rr' seems to represent a revision number - 0, if not given); the corresponding Western Digital numbers are xxxxy, etc (where the 'x's are digits, and the 'y' a letter). The Data Path chip is a 1611H (various DEC part numbers), and the Control chip is a 2007C (ditto); the uROM chips are all 30xxy.

The following sets (Data, Control, uROMs) have been observed (the first three on dual cards):

  • 1611H 21-11549-01, 2007C 23-002C4, 3010A 23-001B5, 3007D 23-002B5
  • 1611H 21-16890, 2007C 23-002C4, 3010D 23-001B5, 3007D 23-007B5
  • 1611H 21-16890, 2007C 23-003C4, 3010D 23-008B5, 3007D 23-007B5
  • unknown, unknown, 3010D 23-001B5, 3007D 23-002B5

The 3010D contains uROM addresses 0x000-0x1ff, and the 3007D 23-002B5 contains 0x200-0x3ff.

For the KEV11-B, one version is known, the 23-090A5; it is suitable for the M7270 quad module etch revisions C and D.

The KEV11-C uses two uROMs, the 3025D 23-004B5 and 3026D (perhaps B?) 23-005B5. (There may also be a hybrid - i.e. single DIP carrier - version of the KEV11-C, but the part number is unknown.)

The version of the KEV11-C option with two uROMs obviously takes two uROM sockets; it is therefore used with a 40-pin hybrid (two chips on one carrier) which holds the two uROMs of the base instruction set. The hybrid is 23-001B6, 23-002B6, or 23-003B6 (for M7264 ECO 10, ECO 12, and ECO 16, respectively).

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