FP11 floating point

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FP11 floating point is the term used for the floating point data types and instructions supported by most PDP-11s which had hardware support for floating point. (Some supported a simpler, less capable floating point capability, the FIS floating point.) It was tightly integrated with the CPU, so that the CPU processed a mix of 'regular' and floating point instructions.


FP11-type floating point supported short (32 bit) and long (64 bit) floating point numbers; both forms used an 8 bit exponent (in 'excess 0200' notation, giving an exponent range of +127. to -128.), a sign bit, and the remaining bits were the fractional part. It also supported short (16 bit) and long (32 bit) integers. State bits controlled whether it operated in short or long mode for each, and whether floating results were rounded, or 'chopped' (DEC's term for truncated, to avoid confusion with series truncation).

It provided the usual range of arithmetic operations, as well as conversion to and fro between floating point and integer representations. Checking for underflow. overflow, and a variety of other situations (e.g. division by zero) was performed in hardware, and optionally could cause an interrupt if they happened; condition code bits, analagous to those for integer operations in the main CPU, recorded the outcome of operations.

It contained 6 internal registers, each capable of holding either a short or long floating point value. The instruction format resembled other PDP-11 instructions, in that all the usual addressing modes could be used with the normal registers to load and store floating point data from/to memory.


The initial implementation was the FP11-B Floating-Point Processor for the KB11-A CPU for the PDP-11/45; it was later used in the KB11-B CPU of the PDP-11/70. Later implementations included: