FPJ11 floating point accelerator

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The FPJ11 floating point accelerator is an optional floating point co-processor for the DCJ11 J-11 PDP-11 chip, which implements the full FP11 floating point instruction set. The FPJ11 is a single chip which is plugged into a socket on a J-11 CPU card.

Although the DCJ11 contains a full implementation of the FP11 floating point instructions, in microcode, if a J-11 CPU board has an FPJ11 installed, the DCJ111 will automatically notice the presence of the FPJ11, and allow it to handle all floating-point instructions.

Addition of the FPJ11 improves floating-point peformance by a factor of 5 to 8. The interface between the DCJ11 and the FPJ11 is designed to allow overlap between execution of floating point instructions in the FPJ11, and execution of non-floating point instructions in the DCJ11.


Two versions of the FPJ11 exist; the FPJ11-AA and the FPJ11-AB. DEC had a number of problems with 'corner cases' (e.g. DMA during certain floating point instructions), and had to issue revised versions of the FPJ11 and some J-11 CPU boards (e.g. the KDJ11-A to fix them all.

Further reading

  • uNote #025, "FPJ11-AA Compatibility with the LSI-11/73 (KDJ11-A)", 28 April 1985
  • uNote #040, "FPJ11 Theory of Operation", 17 September 1985