- KDJ11-A CPU - M8192 - QBUS dual-width CPU
- KDJ11-B CPU - M8190 - QBUS quad-width CPU used in the PDP-11/83 and PDP-11/84
- KDJ11-E CPU - M8981 - QBUS quad-width CPU used in the PDP-11/93 and PDP-11/94
All the KDJ11 CPUs except early revisions of the KDJ11-A CPU have two choices for floating point support (full FP11 floating point): the base DCJ11 chip, which implements floating point using microcode; and an optional higher-performance separate dedicated chip, the FPJ11.
The J-11 chip set includes microcode which provides 'front panel' functionality named 'ODT'; the ability to read and write to memory, start the process, etc. Unlike the ODT in the KDF11 CPUs, which only supported 18-bit addressing, the KDJ11's do not have this limitation.
Note, however, that the KDJ11-A and KDJ11-B power up with the cache enabled, even for ODT, so if the user writes some data into a given location using ODT, and then reads it back, they will get the correct data even if that memory location is faulty - the CPU is getting the (correct) data from the cache.
To have 'memory' reads and writes actually go to the memory, the cache has to be turned off:
Note that starting the machine does an INIT, which will again enable the cache.
- uNote #025, "FPJ11-AA Compatibility with the LSI-11/73 (KDJ11-A)", 28 April 1985
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