J-11 chip set

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J-11

The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.

It implements the full PDP-11 Memory Management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating-point support (using microcode), it can operate with an FPJ11 floating point accelerator chip.

Most uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.