J-11 chip set
The J-11 (formally, the DCJ11, although DEC documentation uses both names) is a high-performance CMOS implementation of the PDP-11 architecture, implemented in two chips ('Control' and 'Data') carried on a single 60-pin DIP carrier.
It implements the full PDP-11 Memory Management architecture (with split Instruction and Data address space support, as well as Supervisor mode). Although it contains built-in FP11 floating-point support (using microcode), it can operate with an FPJ11 floating point accelerator chip.
Most uses on DEC PDP-11 CPU boards (all for the QBUS) contain an external cache.
|v • d • ePDP-11 Computers and Peripherals|
| Unibus PDP-11s - PDP-11/20 • PDP-11/15 • PDP-11/35 • PDP-11/40 • PDP-11/45 • PDP-11/50 • PDP-11/55 • PDP-11/70 • PDP-11/05 • PDP-11/10 • PDP-11/34 • PDP-11/04 • PDP-11/44 • PDP-11/60 • PDP-11/24 • PDP-11/84 • PDP-11/94
Clones: CM 1420