MK11 memory system
The MK11 memory system was a DRAM main memory system for the PDP-11/70. It was 32 bits wide, to interface to the -11/70's Main Memory Bus, and provided ECC (7 bits/double-word), which could correct single-bit errors. Read, Write, and Exchange cycles were supported.
It came in at least two variants, the MK11-B (which used 16KB and 64KB memory array modules), and the MK11-B-2 (which added the ability to use 256KB modules). (It is not known if there was an MK11-A, and if so, what it was.) A maximum of eight MK11 systems could be installed on a single machine, for a maximum of slightly less than 4MB (with 64KB modules, eight MK11 systems would be needed to reach this; with 265KB modules, only two).
A backplane held a pair of memory bus interface boards (an M8158 address buffer board, and either an M8159 or M8164 data buffer board; the M8159 could only be used with 64KB memory modules, whereas the M8164 could be used with either); two pairs of control boards (an M8160 Control A module, and an M8161 Control B module), one for each side of the MK11 system; and between 1 and 16 memory array modules.
The Control A modules generated timing signals, did module addressing, checked the configuration (below), and did memory refresh. The Control B modules interface to the memory modules, and computer and check the ECC.
The memory array modules were placed in the backplane from the inner slots (next to the buffer and control boards) toward the outer; the buffer and control boards went in the center slots. When an MK11 backplane contained a mix of different size board pairs, the smallest ones had to be in the lower locations (i.e. close to the buffer and control boards). If there were an even number of memory array boards installed, and the sizes were matched on each side, the MK11 automatically enabled interleaving.
An MK11-B could be upgraded to an MK11-B-2 by swapping in an M8164 data buffer board for the M8159, and swapping in, or adding, pairs of 256KB board sets.
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Clones: CM 1420