MK11 memory system
The MK11 memory system was a DRAM main memory system for the PDP-11/70. It was 32 bits wide, to interface to the -11/70's Main Memory Bus, and provided ECC (7 bits/double-word), which could correct all single-bit errors. Read, Write, and Exchange cycles were supported. It came in at least three variants:
- the MK11-B (which used 16KB and 64KB MS11-K MOS memory array modules)
- the MK11-B-2 (which added the ability to use 256KB memory array modules).
- the MKA11 (a multi-port memory version for the PDP-11/74)
(It is not known if there was an MK11-A, and if so, what it was.)
A maximum of eight MK11 systems could be installed on a single machine, for a maximum of slightly less than 4MB (with 64KB modules, eight MK11 systems would be needed to reach this; with 265KB modules, only two).
An MK11 system contained six hex control modules (of four different types), and then a group of hex memory array modules; they were housed in a BA11-K mounting box, and plugged into a large custom backplane. A separate control panel module mounted in the rack controlled whether the MK11 unit was in use, what its starting address was, etc.
A backplane held a pair of memory bus interface boards (an M8158 address buffer board, and either an M8159 or M8164 data buffer board; the M8159 could only be used with 64KB memory modules, whereas the M8164 could be used with either those or 256KB modules); two pairs of control boards (an M8160 Control A module, and an M8161 Control B module), one for each side of the MK11 system; and between 1 and 16 memory array modules.
The Control A modules generated timing signals, did module addressing, checked the configuration (below), and did memory refresh. The Control B modules interfaced to the memory modules, and computed and checked the ECC.
The memory array modules were placed in the backplane from the inner slots (next to the buffer and control boards) toward the outer; the buffer and control boards went in the center slots.
When an MK11 backplane contained a mix of different size board pairs, the smallest ones had to be in the lower locations (i.e. close to the buffer and control boards). If there were an even number of memory array boards installed, and the sizes were matched on each side, the MK11 automatically enabled interleaving.
The MKA11 added two other control boards: the M8162 Port MUX A module, and the M8163 Port MUX B module.
An MK11-B could be upgraded to an MK11-B-2 by swapping in an M8164 data buffer board for the M8159, and swapping in, or adding, pairs of 256KB board sets.
There were two generations of memory array modules for the MK11; the first is the MS11-K (above); the second is the M8728 (name currently unknown), which used 156 16Kx1 DRAM chips to provide a 256KB memory array module.
A later board, the M8750, used the same PCB as the M8728, but 64Kx1 DRAM chips - the board had jumpers to allow the use of either size chip - to provide a 1MB memory array module (used in the VAX-11/730 and VAX-11/750).
This board was not supported by the MK11. However, it is possible to use them in an MK11, with slight modifications (see the message linked below for the details).
Also, it is theorized that with the appropriate jumper configuration, they can be made to look like 256KB boards; this will 'waste' 3/4 of the storage on the card, but if 256KB boards are unobtainable, the fairly widely-available M8750's could be substituted.
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