Difference between revisions of "KS10"
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| manufacturer = [[Digital Equipment Corporation]] | | manufacturer = [[Digital Equipment Corporation]] | ||
| architecture = [[PDP-10]] | | architecture = [[PDP-10]] | ||
| − | + | | year introduced = 1978 | |
| − | |||
| form factor = small [[mainframe]] | | form factor = small [[mainframe]] | ||
| word size = 36 bits | | word size = 36 bits | ||
| Line 11: | Line 10: | ||
| logic type = [[LS TTL]] [[IC]]s | | logic type = [[LS TTL]] [[IC]]s | ||
| design type = clocked synchronous [[microcode]]d | | design type = clocked synchronous [[microcode]]d | ||
| + | | uword width = 96 | ||
| + | | ucode length = 2K words | ||
| clock speed = 20 MHz | | clock speed = 20 MHz | ||
| + | | cache size = 512 words | ||
<!-- | memory speed = 1.0 μsec (fast), 1.8 μsec (slow) --> | <!-- | memory speed = 1.0 μsec (fast), 1.8 μsec (slow) --> | ||
| memory mgmt = [[paging]], 512-word pages | | memory mgmt = [[paging]], 512-word pages | ||
Revision as of 00:42, 20 October 2017
| KS10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Introduced: | 1978 |
| Form Factor: | small mainframe |
| Word Size: | 36 bits |
| Logic Type: | LS TTL ICs |
| Design Type: | clocked synchronous microcoded |
| Microword Width: | 96 |
| Microcode Length: | 2K words |
| Clock Speed: | 20 MHz |
| Cache Size: | 512 words |
| Physical Address Size: | 19 bits (some had 20) |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TOPS-20, ITS |
| Predecessor(s): | KL10 |
| Successor(s): | None |
The KS10 was the fourth and last generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of LS TTL chips, along with AMD 2901 bit slice chips, on four super hex cards.
