Difference between revisions of "KA10"
From Computer History Wiki
m (link t/s) |
m (+cat, fix links) |
||
| Line 7: | Line 7: | ||
| form factor = [[mainframe]] | | form factor = [[mainframe]] | ||
| word size = 36 bits | | word size = 36 bits | ||
| − | | physical address = 18 bits (normal), 19/20 ([[ITS]] paging box), ?? ([[TENEX]] paging box) | + | | physical address = 18 bits (normal), 19/20 ([[Incompatible Timesharing System|ITS]] paging box), ?? ([[TENEX]] paging box) |
| virtual address = 18 bits | | virtual address = 18 bits | ||
| logic type = silicon [[transistor]]s and diodes | | logic type = silicon [[transistor]]s and diodes | ||
| Line 14: | Line 14: | ||
| memory speed = 1.0 μsec (fast), 1.8 μsec (slow) | | memory speed = 1.0 μsec (fast), 1.8 μsec (slow) | ||
| memory mgmt = dual [[base and bounds]] register pairs (non-customized machines) | | memory mgmt = dual [[base and bounds]] register pairs (non-customized machines) | ||
| − | | operating system = Monitor, | + | | operating system = Monitor, ITS, TENEX |
| predecessor = [[PDP-6]] | | predecessor = [[PDP-6]] | ||
| successor = [[KI10]] | | successor = [[KI10]] | ||
| Line 27: | Line 27: | ||
It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]]. | It was also the machine on which the [[ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[paging]]. | ||
| + | |||
| + | [[Category:DEC CPUs]] | ||
Revision as of 13:47, 20 October 2017
| KA10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | January, 1966 |
| Year First Shipped: | September, 1967 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | silicon transistors and diodes |
| Design Type: | asynchronous with hardware subroutines |
| Clock Speed: | 3 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous) |
| Memory Speed: | 1.0 μsec (fast), 1.8 μsec (slow) |
| Physical Address Size: | 18 bits (normal), 19/20 (ITS paging box), ?? (TENEX paging box) |
| Virtual Address Size: | 18 bits |
| Memory Management: | dual base and bounds register pairs (non-customized machines) |
| Operating System: | Monitor, ITS, TENEX |
| Predecessor(s): | PDP-6 |
| Successor(s): | KI10 |
| Price: | US$150K (CPU), US$300-700K (system) |
B-series FLIP CHIP used in the KA10 CPU
The KA10 was the first generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of discrete transistors, on short single FLIP CHIP cards.
It had hardware support for time-sharing (two modes, 'User' and 'Executive'), as well as base and bounds memory management hardware. These were used in the first DECsystem-10 models, running TOPS-10.
It was also the machine on which the ITS and TENEX operating systems were developed, after the machines were modified to provide paging.
