Difference between revisions of "KL10"
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| − | The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[ECL]], on [[DEC card form factor|hex]] cards. It was the first [[Microcode|microprogrammed]] PDP-10 processor; the design was inspired by Stanford's [[Superfoonly]]. | + | The '''KL10''' was the third generation of [[PDP-10]] processors. It was built out of [[Emitter-coupled logic|ECL]], on [[DEC card form factor|hex]] cards. It was the first [[Microcode|microprogrammed]] PDP-10 processor; the design was inspired by Stanford's [[Superfoonly]]. |
| − | The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' ('Memory'). It provided three types of [[bus]]ses to the rest of the components of the system; the 'E Bus', from the E Box; and the 'S Bus' ('Storage'), and later the 'C Bus' ('Channel'), from the M Box. The S Bus was for the attachment of [[main memory]] units (it was later upgraded to something called the 'X Bus'), while the C Bus alowed [[Direct Memory Access|DMA]] accesss to main memory. | + | The [[Central Processing Unit|CPU]] had two main units, the 'E Box' ('Execution') and the 'M Box' ('Memory'). It provided three types of [[bus]]ses to the rest of the components of the system; the 'E Bus', from the E Box; and the 'S Bus' ('Storage'), and later the 'C Bus' ('[[Channel]]'), from the M Box. The S Bus was for the attachment of [[main memory]] units (it was later upgraded to something called the 'X Bus'), while the C Bus alowed [[Direct Memory Access|DMA]] accesss to main memory. |
Up to 4 [[DTE20 Interface]]s (which allowed connection of a [[PDP-11]] [[front end]]), and up to 8 [[RH20 MASSBUS controller]]s could be connected to the E Bus (the latter were also connected to the C Bus). At least one PDP-11, the 'master', was required; it could [[bootstrap]] the KL10, including loading the [[microcode]]. | Up to 4 [[DTE20 Interface]]s (which allowed connection of a [[PDP-11]] [[front end]]), and up to 8 [[RH20 MASSBUS controller]]s could be connected to the E Bus (the latter were also connected to the C Bus). At least one PDP-11, the 'master', was required; it could [[bootstrap]] the KL10, including loading the [[microcode]]. | ||
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* CPU hardware variants (PA and PV); | * CPU hardware variants (PA and PV); | ||
| − | + | * informal internal names for CPU variations ('Model A' and 'Model B'); | |
| − | * informal internal names for CPU variations ('Model A' and 'Model B'). | + | * KL10 'models' (-A through -E). |
The later KL10-PV supported the 'Extended' PDP-10 [[architecture]], with support for multiple 'sections' (256K-[[word]] [[address space]]s), available to both the [[kernel]] and the [[user]] (although apparently only [[TOPS-20]] supported the latter). The earlier machines could be field upgraded to a -PV, but it needed a new [[backplane]]. | The later KL10-PV supported the 'Extended' PDP-10 [[architecture]], with support for multiple 'sections' (256K-[[word]] [[address space]]s), available to both the [[kernel]] and the [[user]] (although apparently only [[TOPS-20]] supported the latter). The earlier machines could be field upgraded to a -PV, but it needed a new [[backplane]]. | ||
| + | |||
| + | There is currently a lack of clarity aout the [[MCA25 KL Cache/Paging Upgrade]], which increased the size of both the main memory [[cache]], and the [[Virtual memory|paging]] cache, as well as improved the functionality of the latter. Some sources indicate that it too required a new backplane, becoming the 'Model C'. | ||
As far as is known, 'Model A' is an internal aphorism for -PA, and | As far as is known, 'Model A' is an internal aphorism for -PA, and | ||
| − | 'Model B' for -PV. | + | 'Model B' for -PV; the two are described in a DEC document as: |
| + | |||
| + | * "KL10-PA - A basic ECL processor with slots for cache and internal channels. Unofficially .. referred to as the Model A machine." | ||
| + | * "KL10-PV - A KL10-PA which has been modified to include extended addressing, more extensive microcode, and a faster [[clock]]. Unofficially .. referred to as the Model B machine." | ||
Many of the 'models' (e.g. 'KL10-C' and 'KL10-D') appear to be names for particular configurations (with various options, such as the DMA20 and DIA20); here is a DEC table which (hopefully authoritatively) defines them: | Many of the 'models' (e.g. 'KL10-C' and 'KL10-D') appear to be names for particular configurations (with various options, such as the DMA20 and DIA20); here is a DEC table which (hopefully authoritatively) defines them: | ||
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The DEC numeric model numbers - a fourth namespace - are even more confused, since a 1090 could be either a "KL10-B(PA) or KL10-D(PV)"; similarly, the 2040 and 2050 could be a "KL10-C(PA) or KL10-E(PV)". | The DEC numeric model numbers - a fourth namespace - are even more confused, since a 1090 could be either a "KL10-B(PA) or KL10-D(PV)"; similarly, the 2040 and 2050 could be a "KL10-C(PA) or KL10-E(PV)". | ||
| − | The 'KL10-R' appears to be a Model E in a new cabinet design, one compliant with newer FCC [[noise|RFI]] emissions standards. | + | The 'KL10-R' appears to be a Model E in a new cabinet design, one compliant with newer FCC [[noise|RFI]] emissions standards, but it may also refer to systems with the MCA25. |
==Well-known KL10's== | ==Well-known KL10's== | ||
| − | There was a single KL10 [[Incompatible Timesharing System|ITS]] machine, MIT-MC. It was later renamed to MX after a [[KS10]] took the 'MC' identity, and was finally shut down in 1988; it is now in storage at the [[Living Computers Museum]]. There was also a KL10 in the [[Stanford | + | There was a single KL10 [[Incompatible Timesharing System|ITS]] machine, MIT-MC. It was later renamed to MX after a [[KS10]] took the 'MC' identity, and was finally shut down in 1988; it is now in storage at the [[Living Computers Museum]]. There was also a KL10 in the [[Stanford Artificial Intelligence Laboratory|SAIL]] [[WAITS]] system. |
==External Links== | ==External Links== | ||
Revision as of 15:33, 8 July 2019
| KL10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | January, 1972 |
| Year First Shipped: | June, 1975 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | ECL ICs |
| Design Type: | clocked synchronous, microcoded |
| Microword Width: | 80 |
| Microcode Length: | 1280 (Model A) 2K (Model B) |
| Clock Speed: | 500 nsec |
| Cache Size: | 2K words |
| Memory Speed: | 1.0 μsec (initial core memory), 500 nsec (later MOS main memory) |
| Physical Address Size: | 22 bits |
| Virtual Address Size: | 18 bits (Model A and B) 23 bits (Model E) |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TOPS-20, ITS, WAITS, TENEX, TYMCOM-X |
| Predecessor(s): | KI10 |
| Successor(s): | none |
| Price: | US$250K (CPU), US$600K-1.2M (system) |
The KL10 was the third generation of PDP-10 processors. It was built out of ECL, on hex cards. It was the first microprogrammed PDP-10 processor; the design was inspired by Stanford's Superfoonly.
The CPU had two main units, the 'E Box' ('Execution') and the 'M Box' ('Memory'). It provided three types of busses to the rest of the components of the system; the 'E Bus', from the E Box; and the 'S Bus' ('Storage'), and later the 'C Bus' ('Channel'), from the M Box. The S Bus was for the attachment of main memory units (it was later upgraded to something called the 'X Bus'), while the C Bus alowed DMA accesss to main memory.
Up to 4 DTE20 Interfaces (which allowed connection of a PDP-11 front end), and up to 8 RH20 MASSBUS controllers could be connected to the E Bus (the latter were also connected to the C Bus). At least one PDP-11, the 'master', was required; it could bootstrap the KL10, including loading the microcode.
A DMA20 Memory Bus Controller could be attached to the S Bus, to provide an external memory bus (compatible with the earlier KA10 and KI10). Similarly, an DIA20 In/Out Bus Controller could be attached to the E Bus, to provide a KA10/KI10 compatible I/O bus.
The KL10 was used in the DECsystem-10 models 108x and 109x systems (initially with an external memory bus), and in the high-end 20xx systems of the DECSYSTEM-20 line (with an internal memory bus).
Like its predecessor, the KI10, it was initially released in a single-processor version; a two-CPU version was released later.
Versions
There were a number of variants over the lifetime of the KL10; the situation is confusing because there appear to be three different, somewhat orthogonal, namespaces for KL10 Variants:
- CPU hardware variants (PA and PV);
- informal internal names for CPU variations ('Model A' and 'Model B');
- KL10 'models' (-A through -E).
The later KL10-PV supported the 'Extended' PDP-10 architecture, with support for multiple 'sections' (256K-word address spaces), available to both the kernel and the user (although apparently only TOPS-20 supported the latter). The earlier machines could be field upgraded to a -PV, but it needed a new backplane.
There is currently a lack of clarity aout the MCA25 KL Cache/Paging Upgrade, which increased the size of both the main memory cache, and the paging cache, as well as improved the functionality of the latter. Some sources indicate that it too required a new backplane, becoming the 'Model C'.
As far as is known, 'Model A' is an internal aphorism for -PA, and 'Model B' for -PV; the two are described in a DEC document as:
- "KL10-PA - A basic ECL processor with slots for cache and internal channels. Unofficially .. referred to as the Model A machine."
- "KL10-PV - A KL10-PA which has been modified to include extended addressing, more extensive microcode, and a faster clock. Unofficially .. referred to as the Model B machine."
Many of the 'models' (e.g. 'KL10-C' and 'KL10-D') appear to be names for particular configurations (with various options, such as the DMA20 and DIA20); here is a DEC table which (hopefully authoritatively) defines them:
| Model | PV | Cache | Int Chans | Max DTEs | Max RH20s | DIA | DMA |
|---|---|---|---|---|---|---|---|
| KL10-A | No | Yes | No | 1 | 0 | Yes | Yes |
| KL10-B | No | Yes | Yes | 4 | 8 | Yes | Yes |
| KL10-C | No | Optional | Yes | 4 | 8 | No | No |
| KL10-D | Yes | Yes | Yes | 4 | 8 | Yes | Yes |
| KL10-E | Yes | Optional | Yes | 4 | 8 | * | No |
(The meaning of the '*' is not clear.)
This table does illustrate one enduring query: in terms of actual CPU hardware variants, it was throught that the early 'Model A' only supported a single DTE20, and no RH20s (the latter possibly as it had no C Bus), and it was the later 'Model B' KL10 which supported up to 4 DTE20s and up to 8 RH20s (along with a larger microcode store, and extended addressing).
However, the table appears to show that the KL10-B and KL10-C, both apparently PA machines, did support the larger I/O configuration. The answer is unknown; perhaps the Model A backplane would support them, but not the CPU board set in the KL10-A?
One significant division between KL-based systems is between those with an external memory bus, and those with an internal memory bus (the native S Bus).
The DEC numeric model numbers - a fourth namespace - are even more confused, since a 1090 could be either a "KL10-B(PA) or KL10-D(PV)"; similarly, the 2040 and 2050 could be a "KL10-C(PA) or KL10-E(PV)".
The 'KL10-R' appears to be a Model E in a new cabinet design, one compliant with newer FCC RFI emissions standards, but it may also refer to systems with the MCA25.
Well-known KL10's
There was a single KL10 ITS machine, MIT-MC. It was later renamed to MX after a KS10 took the 'MC' identity, and was finally shut down in 1988; it is now in storage at the Living Computers Museum. There was also a KL10 in the SAIL WAITS system.
