Difference between revisions of "KD11-K CPU"

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The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used the [[UNIBUS]] for [[main memory]] access (although a built-in [[cache]] was standard).
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The '''KD11-K''' was the [[Central Processing Unit|CPU]] of the [[PDP-11/60]]. It provided the [[PDP-11 Memory Management|subset PDP-11 memory management]], and used a [[UNIBUS]] for its [[main memory]] access (although a built-in [[cache]] was standard).
  
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It consisted of a custom 14-slot [[backplane]], and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]:
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It provided the full [[FP11 floating point]] using [[microcode]]; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available. Also available were either a User Control Store (1KW of read-write microcode), an Extended Control Store ([[ROM]] microcode), or a Diagnostic Control Store.
  
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* uWord (M7872)
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One unusual aspect was that the CPU's [[backplane]] had a separate UNIBUS connectors for [[input/output|I/O]] activity, and for memory access. The FMPS indicates (pg. 4) that devices that do [[interrupt]]s and [[Direct Memory Access|DMA]] must be connected to the I/O UNIBUS, and not to the memory UNIBUS; but it also indicates (pg. 3) that there is only a single UNIBUS. (Perhaps all the [[bus grant line]]s from the bus arbitration circuitry in the CPU are only connected to the I/O connector?)
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* Decode (M7873)
 
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* Data Path (M7874)
 
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* KT/Cache (M7875)
 
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* Timing (M7876)
 
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* Status (M7827)
 
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for the basic CPU, held in slots 2-7 of the backplane.
 
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It provided the full [[FP11 floating point]] using microcode; as an option, the [[FP11-E Floating Point Processor]], a 4 hex board [[co-processor]] which provided a high-performance implementation, was also available; it used slots 8-11 of the backplane.
 
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A single slot in the backplane, slot 1, is available to hold either a User Control Store (1KW of read-write microcode), an Extended Control Store ([[ROM]] microcode), or a Diagnostic Control Store.
 
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The remaining slots, 12-14, were [[Small Peripheral Controller|SPC]] slots.
 
  
 
==Microcode==
 
==Microcode==
  
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It was a [[microcode]]d CPU, using 48-bit wide micro-words; the [[address space]] of the micro-engine was 2<sup>12</sup> words, divided into 8 blocks. The allocation of the blocks was:
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It was a microcoded CPU, using 48-bit wide micro-words; the [[address space]] of the micro-engine was 2<sup>12</sup> words, divided into 8 blocks. The allocation of the blocks was:
  
 
<ol start="0">
 
<ol start="0">
 
<li>Base instructions</li>
 
<li>Base instructions</li>
 
</ol>
 
</ol>
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# Console an Error log
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# Console and Error log
 
# EIS, Initialization
 
# EIS, Initialization
 
# Floating point
 
# Floating point
Line 33: Line 20:
 
# ECS/UCS
 
# ECS/UCS
  
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{{PDP-11}}
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==Implementation==
 +
 
 +
It consisted of a custom 14-slot backplane (([[DEC part number]] 70-12953), and 6 [[DEC card form factor|hex]] [[printed circuit board|boards]]:
 +
 
 +
* uWord (M7872)
 +
* Decode (M7873)
 +
* Data Path (M7874)
 +
* [[KT11|KT]]/Cache (M7875)
 +
* Timing (M7876)
 +
* Status (M7827)
 +
 
 +
for the basic CPU. They were held in slots 2-7 of the backplane:
 +
 
 +
{| class="wikitable"
 +
! !! colspan="6" | Connector
 +
|-
 +
! Slot !! A !! B !! C !! D !! E !! F
 +
|-
 +
| 1 || colspan="6" style="text-align:center;" | WCS or ECS or DCS (optional)
 +
|-
 +
| 2 || colspan="6" style="text-align:center;" | uWord (M7872)
 +
|-
 +
| 3 || colspan="6" style="text-align:center;" | Decode (M7873)
 +
|-
 +
| 4 || colspan="6" style="text-align:center;" | Data Path (M7874)
 +
|-
 +
| 5 || colspan="6" style="text-align:center;" | KT/Cache (M7875)
 +
|-
 +
| 6 || colspan="6" style="text-align:center;" | Timing (M7876)
 +
|-
 +
| 7 || colspan="6" style="text-align:center;" | Status (M7827)
 +
|-
 +
| 8 || colspan="6" style="text-align:center;" | Floating Point Next Micro-Address (M7878)
 +
|-
 +
| 9 || colspan="6" style="text-align:center;" | Floating Point Exponent (M7879)
 +
|-
 +
| 10 || colspan="6" style="text-align:center;" | Multiplying Network (M7880)
 +
|-
 +
| 11 || colspan="6" style="text-align:center;" | Floating Point ALU (M7881)
 +
|-
 +
| 12 || colspan="2" style="text-align:center;" | Unused || colspan="4" style="text-align:center;" | SPC
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|-
 +
| 13 || colspan="2" style="text-align:center;" | Memory UNIBUS/Bootstrap || colspan="4" style="text-align:center;" | SPC
 +
|-
 +
| 14 || colspan="2" style="text-align:center;" | I/O UNIBUS/Terminator || colspan="4" style="text-align:center;" | SPC
 +
|}
 +
 
 +
The optional FPP used slots 8-11 of the backplane; a single slot, slot 1, held the microcode option. The remaining slots in the backplane, 12-14, were [[Small Peripheral Controller|SPC]] slots.
 +
 
 +
{{semi-stub}}
 +
 
 +
==External links==
 +
 +
* [http://www.bitsavers.org/pdf/dec/pdp11/1160/ PDP-11/60] - BitSavers
 +
** [http://www.bitsavers.org/pdf/dec/pdp11/1160/EK-KD11K-TD-PRE_Jan78.pdf KD11K Processor (11/60) Technical Description Manual - Maintenance Features] (EK-KD11K-TD-PRE)
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** [http://www.bitsavers.org/pdf/dec/pdp11/1160/1160_Microprogramming_Specification_1977.pdf 11/60 Microprogramming Specification]
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** [http://www.bitsavers.org/pdf/dec/pdp11/1160/MP00409_1160cpu_KD11-K.pdf 11/60 Basic Field Maintenance Print Set] (MP00409)
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** [http://www.bitsavers.org/pdf/dec/pdp11/1160/MP00500_1160WCS_Nov77.pdf KU116-AA Field Maintenance Print Set] (MP00500)
  
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[[Category: PDP-11 Processors]]
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[[Category: PDP-11 UNIBUS Processors]]
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[[Category: UNIBUS Processors]]
 

Latest revision as of 11:34, 11 October 2022

The KD11-K was the CPU of the PDP-11/60. It provided the subset PDP-11 memory management, and used a UNIBUS for its main memory access (although a built-in cache was standard).

It provided the full FP11 floating point using microcode; as an option, the FP11-E Floating Point Processor, a 4 hex board co-processor which provided a high-performance implementation, was also available. Also available were either a User Control Store (1KW of read-write microcode), an Extended Control Store (ROM microcode), or a Diagnostic Control Store.

One unusual aspect was that the CPU's backplane had a separate UNIBUS connectors for I/O activity, and for memory access. The FMPS indicates (pg. 4) that devices that do interrupts and DMA must be connected to the I/O UNIBUS, and not to the memory UNIBUS; but it also indicates (pg. 3) that there is only a single UNIBUS. (Perhaps all the bus grant lines from the bus arbitration circuitry in the CPU are only connected to the I/O connector?)

Microcode

It was a microcoded CPU, using 48-bit wide micro-words; the address space of the micro-engine was 212 words, divided into 8 blocks. The allocation of the blocks was:

  1. Base instructions
  1. Console and Error log
  2. EIS, Initialization
  3. Floating point
  4. Floating point
  5. ECS
  6. ECS/UCS
  7. ECS/UCS

Implementation

It consisted of a custom 14-slot backplane ((DEC part number 70-12953), and 6 hex boards:

  • uWord (M7872)
  • Decode (M7873)
  • Data Path (M7874)
  • KT/Cache (M7875)
  • Timing (M7876)
  • Status (M7827)

for the basic CPU. They were held in slots 2-7 of the backplane:

Connector
Slot A B C D E F
1 WCS or ECS or DCS (optional)
2 uWord (M7872)
3 Decode (M7873)
4 Data Path (M7874)
5 KT/Cache (M7875)
6 Timing (M7876)
7 Status (M7827)
8 Floating Point Next Micro-Address (M7878)
9 Floating Point Exponent (M7879)
10 Multiplying Network (M7880)
11 Floating Point ALU (M7881)
12 Unused SPC
13 Memory UNIBUS/Bootstrap SPC
14 I/O UNIBUS/Terminator SPC

The optional FPP used slots 8-11 of the backplane; a single slot, slot 1, held the microcode option. The remaining slots in the backplane, 12-14, were SPC slots.

External links

Retrieved from "https://gunkies.org/w/index.php?title=KD11-K_CPU&oldid=27798"