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The PDP-11/60 was, in its day, a rather unsuccessful model of DEC's PDP-11 line; although considerable more complex than the PDP-11/34, it did not have significant capability advantages over it.

In particular, it had the same limited memory management, without so-called 'I+D separatation', which therefore limited the size of the applications which could run on it; it also supported only the UNIBUS, which normally limited it to 248KB of main memory.

It is of interest now since it had an option to permit loadable microcode; it is a very rare machine, though, since its lack of commercial success meant very few were produced.


The PDP-11/60 is based around the KD11-K CPU. It provided the full FP11 floating point using microcode; as an option, the FP11-E Floating Point Processor, which provided a high-performance implementation as a co-processor, was also available.

A single slot in the CPU's backplane is available to hold either a User Control Store (1KW of read-write microcode), an Extended Control Store (1.5KW ROM microcode), or a Diagnostic Control Store.

Standard main memory was either MM11-WP core memory, or MF11S-KF MOS Memory.

The -11/60 used swing-out BA11-P card cages to hold all its cards; generally a pair, one holding the CPU and device controllers, the other main memory and more controllers.


Front console of a PDP-11/60

1977. The /60 was an expensive "middle-class" machine, intended as the successor of the /40. It should have been introduced after the /70, but was delayed at least 12-18 months due design and debugging problems. It had a writable control store (WCS) for custom instructions, and floating point instructions were implemented in the CPU microcode. It also had 18-bit memory management. With the FPP option it had the best floating point performance among the -11's. As for packaging, it came in the "low boy/high boy" cabinets, the one pictured to the left is the "high" one. The storage devices could be placed in the upper region, the card cage itself was in the lower half.

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