Difference between revisions of "PDP-15"

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| logic type = [[Transistor-transistor logic|TTL]] [[Integrated circuit|IC]]s
 
| logic type = [[Transistor-transistor logic|TTL]] [[Integrated circuit|IC]]s
 
<!--| design type =  asynchronous with hardware subroutines  -->
 
<!--| design type =  asynchronous with hardware subroutines  -->
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| clock speed = 1.6 μsec (basic instructions)
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| instruction speed = 1.6 μsec (basic)
 
| memory speed = 0.8 μsec
 
| memory speed = 0.8 μsec
 
| memory mgmt = bounds register; [[base and bounds]] pair (both optional)
 
| memory mgmt = bounds register; [[base and bounds]] pair (both optional)
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}}
 
}}
  
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The '''PDP-15''' was [[Digital Equipment Corporation|DEC]]'s last 18-bit computer, and the only one implemented using [[integrated circuit]]s. Its principal intended use was for [[real-time system]]s. A variety of models were offered, from the PDP-15/10 (with 4K words of [[main memory]]), to the PDP-15/40 (with 24K words, and two [[disk]]s).
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The '''PDP-15''' was [[Digital Equipment Corporation|DEC]]'s last 18-bit computer, and the only one implemented using [[integrated circuit]]s. Its principal intended use was for [[real-time system]]s. A variety of models were offered, from the PDP-15/10 (with 4K [[word]]s of [[main memory]]), to the PDP-15/40 (with 24K words, and two [[disk]]s).
  
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[[Instruction]]s had a 4-bit opcode, one bit of indirect, and one of indexing. It was a [[load-store architecture]], with a single [[accumulator]]. There were several other specialized [[register]]s, including an 'Index Register', and a 'Limit Register' for [[loop]] control.
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It was a [[load-store architecture]], with a single [[accumulator]]. There were several other specialized [[register]]s, including an 'Index Register', and a 'Limit Register' for [[loop]] control.
  
 
Both multiply/divide and [[floating point]] support were hardware options (the former being standard on all but the lowest model). The FP15 floating point unit was a complete separate processor, but shared the [[instruction set]] space with the basic CPU.
 
Both multiply/divide and [[floating point]] support were hardware options (the former being standard on all but the lowest model). The FP15 floating point unit was a complete separate processor, but shared the [[instruction set]] space with the basic CPU.
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KM15 [[memory management]] included a boundary register to set the boundary between protected and un-protected memory, and two modes for the [[Central Processing Unit|CPU]]. A memory relocation option, the KT15, with a [[base and bounds]] register pair, was also available.
 
KM15 [[memory management]] included a boundary register to set the boundary between protected and un-protected memory, and two modes for the [[Central Processing Unit|CPU]]. A memory relocation option, the KT15, with a [[base and bounds]] register pair, was also available.
  
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A large range of [[peripheral]]s were available, including [[DECtape]] (via the TC15 controller), [[fixed-head disk]] (RF15 controller), and [[RP02 disk drive|RP02]] large disk (RP15 controller).
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A large range of [[peripheral]]s were available, including [[DECtape]] (via the TC15 controller), [[fixed-head disk]] (RS09 disk via the RF15 controller), and [[RP02 disk drive|RP02]] large [[disk]] (RP15 controller).
  
 
Later models supported an interface (the [[UNICHANNEL 15 System|UNICHANNEL-15]], UC15) to a satellite [[PDP-11]] (usually a [[PDP-11/05]]), through which other PDP-11-native peripherals could be supported, including [[Direct Memory Access|DMA]] directly into the PDP-15's memory through the [[MX15-B Memory Multiplexer]]. These sometimes used the [[UNIBUS]] [[UNIBUS parity#18-bit width|adaption for 18-bit mode]], where the two [[parity]] lines were recycled into 2 extra data lines.
 
Later models supported an interface (the [[UNICHANNEL 15 System|UNICHANNEL-15]], UC15) to a satellite [[PDP-11]] (usually a [[PDP-11/05]]), through which other PDP-11-native peripherals could be supported, including [[Direct Memory Access|DMA]] directly into the PDP-15's memory through the [[MX15-B Memory Multiplexer]]. These sometimes used the [[UNIBUS]] [[UNIBUS parity#18-bit width|adaption for 18-bit mode]], where the two [[parity]] lines were recycled into 2 extra data lines.
  
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==Further Reading==
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==Instructions==
 +
 
 +
[[Instruction]]s had a 4-bit opcode, one bit of indirect, one of indexing, and a 12-bit [[address]] field (which was used together with other information, such as the contents of the Index Register, to form the actual address of the [[operand]]):
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{{18bit-header}}
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| colspan=4 | Opcode || colspan=2 | Mode || colspan=12 | Address
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{{18bit-bitout}}
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Values for the Address Mode ('E') field are:
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{| class="wikitable"
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! Indirect !! Indexed !! Operation
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|-
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| 0 || 0 || Direct
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|-
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| 0 || 1 || Indexed
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|-
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| 1 || 0 || Indirect
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|-
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| 1 || 1 || Indirect-Indexed
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|}
 +
 
 +
Of the 16 possible instructions, 13 used the format above; the other 3 used the non-opcode bits to 'microcode' (in DEC's then-terminology) multiple non-memory reference instructions into a single instruction word.
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{{semi-stub}}
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 +
==Further reading==
  
 
''(All available online through [[BitSavers]].)''
 
''(All available online through [[BitSavers]].)''
  
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* "PDP-15 Systems Reference Manual"
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* ''PDP-15 Systems User's Handbook: Volume I - Processor''
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* "PDP-15 Systems User's Handbook: Volume I - Processor"
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* ''PDP-15 Systems User's Handbook: Volume II - Peripherals''
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* "PDP-15 Systems User's Handbook: Volume II - Peripherals"
 
  
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==External Links==
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==External links==
  
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* [http://www.datormuseum.se/documentation-software/pdp-15-documentation PDP-15 documentation]
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* [http://www.bitsavers.org/pdf/dec/pdp15/ PDP-15] - documentation at [[Bitsavers]]
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** [http://bitsavers.org/pdf/dec/pdp15/hardware/ PDP-15 hardware]
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** [http://www.bitsavers.org/pdf/dec/pdp15/PDP15RefMan.pdf PDP-15 Systems Reference Manual] (DEC-15-BRZA-D)
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* [http://www.vaxarchive.org/hardware/pdp11/pdp15rc.tar PDP-15 reference card] (images in TAR file)
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* [http://www.bitsavers.org/pdf/dec/pdp9/DEC-09-H9ZA-D_RF09_Jul70.pdf RS09 DECdisk System Maintenance Manual]
 +
<!-- * [http://www.datormuseum.se/documentation-software/pdp-15-documentation PDP-15 documentation] -->
 
* [http://simh.trailing-edge.com/docs/advmonsys.pdf Unearthing The PDP-15’s Operating Systems]
 
* [http://simh.trailing-edge.com/docs/advmonsys.pdf Unearthing The PDP-15’s Operating Systems]
  
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{{semi-stub}}
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[[Category: DEC Systems]]
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[[Category: PDP-15s]]
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[[Category:DEC Systems]]
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[[Category: 18-bit Computers]]

Latest revision as of 12:40, 11 July 2023


PDP-15
Manufacturer: Digital Equipment Corporation
Year First Shipped: February, 1970
Form Factor: minicomputer
Word Size: 18 bits
Logic Type: TTL ICs
Instruction Speed: 1.6 μsec (basic)
Memory Speed: 0.8 μsec
Physical Address Size: 17 bits (128K words)
Virtual Address Size: 12 bits (direct), 15 bits (indirect), 17 bits (indexed)
Memory Management: bounds register; base and bounds pair (both optional)
Operating System: DECsys, Keyboard Monitor System, Foreground/Background System, DOS-15, XVM/DOS, XVM/RSX, XVM/MUMPS, Advanced Monitor System
Predecessor(s): PDP-9
Successor(s): None


The PDP-15 was DEC's last 18-bit computer, and the only one implemented using integrated circuits. Its principal intended use was for real-time systems. A variety of models were offered, from the PDP-15/10 (with 4K words of main memory), to the PDP-15/40 (with 24K words, and two disks).

It was a load-store architecture, with a single accumulator. There were several other specialized registers, including an 'Index Register', and a 'Limit Register' for loop control.

Both multiply/divide and floating point support were hardware options (the former being standard on all but the lowest model). The FP15 floating point unit was a complete separate processor, but shared the instruction set space with the basic CPU.

KM15 memory management included a boundary register to set the boundary between protected and un-protected memory, and two modes for the CPU. A memory relocation option, the KT15, with a base and bounds register pair, was also available.

A large range of peripherals were available, including DECtape (via the TC15 controller), fixed-head disk (RS09 disk via the RF15 controller), and RP02 large disk (RP15 controller).

Later models supported an interface (the UNICHANNEL-15, UC15) to a satellite PDP-11 (usually a PDP-11/05), through which other PDP-11-native peripherals could be supported, including DMA directly into the PDP-15's memory through the MX15-B Memory Multiplexer. These sometimes used the UNIBUS adaption for 18-bit mode, where the two parity lines were recycled into 2 extra data lines.

Instructions

Instructions had a 4-bit opcode, one bit of indirect, one of indexing, and a 12-bit address field (which was used together with other information, such as the contents of the Index Register, to form the actual address of the operand):

Opcode Mode Address
00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17

Values for the Address Mode ('E') field are:

Indirect Indexed Operation
0 0 Direct
0 1 Indexed
1 0 Indirect
1 1 Indirect-Indexed

Of the 16 possible instructions, 13 used the format above; the other 3 used the non-opcode bits to 'microcode' (in DEC's then-terminology) multiple non-memory reference instructions into a single instruction word.

Further reading

(All available online through BitSavers.)

  • PDP-15 Systems User's Handbook: Volume I - Processor
  • PDP-15 Systems User's Handbook: Volume II - Peripherals

External links

Retrieved from "https://gunkies.org/w/index.php?title=PDP-15&oldid=30403"