Difference between revisions of "RH11 MASSBUS controller"

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The '''RH11 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily [[PDP-11]]'s.
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The '''RH11 MASSBUS controller''' allowed the interconnection of [[MASSBUS]] devices such as the [[RP04 disk drive|RP04]] to systems with a [[UNIBUS]], primarily on [[PDP-11]]'s.
  
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The RH11 has the capability to operate in 18-bit mode; in this mode (used in the [[UC15]] UNICHANNEL-15 on the [[PDP-15]]), the PA and PB UNIBUS lines are used for data bits 16 and 17.
+
There are three models:
  
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==Second UNIBUS==
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* The '''RH11-AB''' model, the most common version.
 +
* The '''RH11-B''' model; it uses the M9725-YA card, which has an [[Engineering Change Order|ECO]] which involves the two added one-shots in the lower left corner of drawing BCTB; the effect is not known.
 +
* The '''RH11-C''' model; it uses the M9724-YA card, which has an ECO modifying the operation of 'Bus Hog' mode (see below).
 +
 
 +
===Second UNIBUS===
  
 
The RH11 contains connectors and circuitry for two separate UNIBUSes; the second UNIBUS is primarily used on systems with [[multi-port memory]], such as the [[PDP-11/45]].
 
The RH11 contains connectors and circuitry for two separate UNIBUSes; the second UNIBUS is primarily used on systems with [[multi-port memory]], such as the [[PDP-11/45]].
  
−
The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
+
The [[register]]s in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, [[interrupt]]s of the [[Central Processing Unit|CPU]] are only possible via UNIBUS 'A'. (The interrupt grant lines on UNIBUS 'B" are only present on the backplane, they are not routed to any of the cards.) The RH11 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B').
 +
 
 +
If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] [[bus grant]]s.
 +
 
 +
The 'A' UNIBUS has a mode where it can do two DMA cycles per grant. The 'B' UNIBUS can operate in so-called 'Bus Hog' mode (enabled by a [[jumper]]); in this mode, the RH11 can do block transfers without going through any UNIBUS [[arbitration]] cycles. (See Section 4.12.10, "BUS HOG Mode", pg. 4-22
 +
[59 of the PDF] in the "RH11-AB Option Description" for details.) The RH11-C ECO breaks such blocks up into 16-word groups.
 +
 
 +
===18-bit mode===
  
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If no CPU is connected to UNIBUS 'B', an [[M9300 terminator]] at the start of the bus can be configured to do [[Non-Processor Request|NPR]] grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle; the 'A' UNIBUS has a mode where it does two DMA cycles per grant.
+
The RH11 has the capability to operate in [[UNIBUS parity#18-bit width|18-bit mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[PDP-15]] and [[KS10]] made use of this capability, the latter with the RH11-C model.
 +
 
 +
Note that 18-bit mode is only available on the 'B' UNIBUS (which must be selected) if a [[jumper]] is removed; see Section 4.16 "Logic Diagram DBCE", pg. 4-28 (65 of the PDF) in the "RH11-AB Option Description" for details.
  
 
==Registers==
 
==Registers==
  
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The RH11 contains 4 registers, plus a share of a fifth; they are
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The RH11 contains 4 [[register]]s, plus a share of a fifth; they are
  
 
* RHCS1 - Control and Status 1 (shared)
 
* RHCS1 - Control and Status 1 (shared)
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==Hardware==
 
==Hardware==
  
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The RH11 consisted of a double [[system unit]] [[backplane]] into which plugged a number of cards:
+
The RH11 consisted of a double [[system unit]] [[backplane]] (below) into which plugged a number of cards:
  
 
Two of them [[DEC card form factor|hex]]-sized:
 
Two of them [[DEC card form factor|hex]]-sized:
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* M7295 - BCT - Bus Control
 
* M7295 - BCT - Bus Control
  
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Two [[DEC card form factor|dual]]-sized cards containing controller logic:
+
Two dual-sized cards containing controller logic:
  
 
* M7296 - CSR - Control and Status
 
* M7296 - CSR - Control and Status
 
* M7297 - PAC - Parity Generation and Checking
 
* M7297 - PAC - Parity Generation and Checking
  
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Three [[DEC card form factor|dual]]-height M5904 MASSBUS transceiver modules.
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Three dual-height M5904 MASSBUS transceiver modules.
  
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Optionally one or two (see below) [[DEC card form factor|single]]-height cards:
+
Optionally one or two single-height cards:
  
 
* M688 - UNIBUS Power Fail Driver
 
* M688 - UNIBUS Power Fail Driver
  
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The RH11 backplane also contained three [[Small Peripheral Controller|SPC]] slots in otherwise-unused slots.
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The RH11 backplane also contained three [[Small Peripheral Controller|SPC]] slots in otherwise-unused slots; they are on UNIBUS 'A'. The NPG [[bus grant line]] is routed through those slots, so they are fully capable.
 +
 
 +
===Backplane layout===
 +
 
 +
Board locations (as seen from the board insertion side of the backplane, not the [[wire-wrap]] pin side, as is common in [[DEC]] documentation) are:
 +
 
 +
{| class="wikitable"
 +
! !! colspan="6" | Connector
 +
|-
 +
! Slot !! A !! B !! C !! D !! E !! F
 +
|-
 +
| 1 || colspan="2" style="text-align:center;" | UNIBUS A In || colspan="2" style="text-align:center;" | M7297 Parity || colspan="2" style="text-align:center;" | M7296 Control/Status
 +
|-
 +
| 2 || colspan="6" style="text-align:center;" | M7295 Bus Control
 +
|-
 +
| 3 || colspan="6" style="text-align:center;" | M7294 Data/Buffer Control
 +
|-
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| 4 || colspan="2" style="text-align:center;" | Unused || colspan="2" style="text-align:center;" | M5904 Transceiver || M688 - UNIBUS B Power Fail || Unused
 +
|-
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| 5 || colspan="2" style="text-align:center;" | Unused || colspan="2" style="text-align:center;" | M5904 Transceiver || M688 - UNIBUS A Power Fail || Unused
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|-
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| 6 || colspan="2" style="text-align:center;" | Unused || colspan="2" style="text-align:center;" | M5904 Transceiver || colspan="4" style="text-align:center;" | Unused
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|-
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| 7 || colspan="2" style="text-align:center;" | UNIBUS B Out || colspan="4" style="text-align:center;" | SPC
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|-
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| 8 || colspan="2" style="text-align:center;" | UNIBUS B In || colspan="4" style="text-align:center;" | SPC
 +
|-
 +
| 9 || colspan="2" style="text-align:center;" | UNIBUS A Out || colspan="4" style="text-align:center;" | SPC
 +
|}
 +
 
 +
The order of the UNIBUS 'B' in/out and 'A' out slots is apparently to allow the use of an [[M9200 UNIBUS jumper]] to tie the two UNIBI together. (E.g. in the 'disk' RH11 in the KS10, where the CPU needs access to the device registers, interrupts, etc, which are on UNIBUS 'A', but also has to be connected to UNIBUS 'B', for 18-bit data transfers.)
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 +
==External links==
 +
 
 +
* [http://www.bitsavers.org/pdf/dec/unibus/ UNIBUS] - BitSavers UNIBUS directory, contains many RH11 documents
 +
** [http://www.bitsavers.org/pdf/dec/unibus/RH11-AB_OptionDescr.pdf RH11-AB/Special Massbus Controller Option Description] (CSS-MO-F-5.2-26)
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** [http://www.bitsavers.org/pdf/dec/unibus/RH11_Peripheral_Controller_Course.pdf RH-11 Peripheral Controller Course Documents] - contains good coverage, including several more complex use cases
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** [http://www.bitsavers.org/pdf/dec/unibus/RH11-AB_Engineering_Drawings_Apr78.pdf RH11 Engineering Drawings]
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** [http://www.bitsavers.org/pdf/dec/unibus/MP00382_RH11-B_schem_Jun77.pdf RH11-B Field Maintenance Print Set] (MP00382)
 +
* [https://manx-docs.org/collections/antonio/arc-db/EY-D3024-WB-001.pdf RH11/RH70 MASSBUS Controllers Self-Paced Course]
 +
* [http://www.bitsavers.org/pdf/dec/disc/rjs03_rjs04/DEC-11-HRJSA-B-D_RJS04_RJS03_fixed-head_disk_system_maintenance_manual_Aug1974.pdf RJS04/RJS03 fixed-head disk system maintenance manual] (DEC-11-HRJSA-B-D) - contains detailed RH11 information
 +
 
 +
[[Category: MASSBUS Controllers]]
 +
[[Category: UNIBUS Storage Controllers]]

Latest revision as of 14:40, 25 February 2022

The RH11 MASSBUS controller allowed the interconnection of MASSBUS devices such as the RP04 to systems with a UNIBUS, primarily on PDP-11's.

There are three models:

  • The RH11-AB model, the most common version.
  • The RH11-B model; it uses the M9725-YA card, which has an ECO which involves the two added one-shots in the lower left corner of drawing BCTB; the effect is not known.
  • The RH11-C model; it uses the M9724-YA card, which has an ECO modifying the operation of 'Bus Hog' mode (see below).

Second UNIBUS

The RH11 contains connectors and circuitry for two separate UNIBUSes; the second UNIBUS is primarily used on systems with multi-port memory, such as the PDP-11/45.

The registers in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, interrupts of the CPU are only possible via UNIBUS 'A'. (The interrupt grant lines on UNIBUS 'B" are only present on the backplane, they are not routed to any of the cards.) The RH11 can be set under software control to do DMA data transfers on either the first or second UNIBUS (UNIBUS 'B').

If no CPU is connected to UNIBUS 'B', an M9300 terminator at the start of the bus can be configured to do NPR bus grants.

The 'A' UNIBUS has a mode where it can do two DMA cycles per grant. The 'B' UNIBUS can operate in so-called 'Bus Hog' mode (enabled by a jumper); in this mode, the RH11 can do block transfers without going through any UNIBUS arbitration cycles. (See Section 4.12.10, "BUS HOG Mode", pg. 4-22 [59 of the PDF] in the "RH11-AB Option Description" for details.) The RH11-C ECO breaks such blocks up into 16-word groups.

18-bit mode

The RH11 has the capability to operate in 18-bit mode; in this mode, the PA and PB UNIBUS parity lines are used for data bits 16 and 17. The PDP-15 and KS10 made use of this capability, the latter with the RH11-C model.

Note that 18-bit mode is only available on the 'B' UNIBUS (which must be selected) if a jumper is removed; see Section 4.16 "Logic Diagram DBCE", pg. 4-28 (65 of the PDF) in the "RH11-AB Option Description" for details.

Registers

The RH11 contains 4 registers, plus a share of a fifth; they are

  • RHCS1 - Control and Status 1 (shared)
  • RHWC - Word Count
  • RHBA - Bus Address
  • RHCS2 - Control and Status 2
  • RHDB - Data Buffer (for maintenance)

As is standard for the MASSBUS, all the other device registers are in the device.

Hardware

The RH11 consisted of a double system unit backplane (below) into which plugged a number of cards:

Two of them hex-sized:

  • M7294 - DBC - Data Buffer and Control
  • M7295 - BCT - Bus Control

Two dual-sized cards containing controller logic:

  • M7296 - CSR - Control and Status
  • M7297 - PAC - Parity Generation and Checking

Three dual-height M5904 MASSBUS transceiver modules.

Optionally one or two single-height cards:

  • M688 - UNIBUS Power Fail Driver

The RH11 backplane also contained three SPC slots in otherwise-unused slots; they are on UNIBUS 'A'. The NPG bus grant line is routed through those slots, so they are fully capable.

Backplane layout

Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:

Connector
Slot A B C D E F
1 UNIBUS A In M7297 Parity M7296 Control/Status
2 M7295 Bus Control
3 M7294 Data/Buffer Control
4 Unused M5904 Transceiver M688 - UNIBUS B Power Fail Unused
5 Unused M5904 Transceiver M688 - UNIBUS A Power Fail Unused
6 Unused M5904 Transceiver Unused
7 UNIBUS B Out SPC
8 UNIBUS B In SPC
9 UNIBUS A Out SPC

The order of the UNIBUS 'B' in/out and 'A' out slots is apparently to allow the use of an M9200 UNIBUS jumper to tie the two UNIBI together. (E.g. in the 'disk' RH11 in the KS10, where the CPU needs access to the device registers, interrupts, etc, which are on UNIBUS 'A', but also has to be connected to UNIBUS 'B', for 18-bit data transfers.)

External links

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