Difference between revisions of "KA10"
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| virtual address = 18 bits | | virtual address = 18 bits | ||
| logic type = silicon [[transistor]]s and diodes | | logic type = silicon [[transistor]]s and diodes | ||
| − | | design type = | + | | design type = asynchronous with hardware subroutines |
| − | | | + | | instruction speed = 3 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous) |
| memory speed = 1.0 μsec (fast), 1.8 μsec (slow) | | memory speed = 1.0 μsec (fast), 1.8 μsec (slow) | ||
| memory mgmt = dual [[base and bounds]] register pairs (non-customized machines) | | memory mgmt = dual [[base and bounds]] register pairs (non-customized machines) | ||
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}} | }} | ||
| − | [[Image:KA10 mod end.jpg|150px|thumb| | + | [[Image:KA10FrontPanel.jpg|thumb|left|300px|The front panel of a KA10]] |
| + | |||
| + | The '''KA10''' was the first generation of [[PDP-10]] [[Central Processing Unit|processors]] (themselves, exact re-implementations of the earlier [[PDP-6]] architecture). It was built out of discrete [[transistor]]s, on [[DEC card form factor|short single]] [[FLIP CHIP]] cards, plugged into large custom-wired [[backplane]]s. | ||
| + | |||
| + | It had hardware support for [[time-sharing]] (two modes, 'User' and 'Executive'), as well as [[base and bounds]] [[memory management]] hardware. These were used in the first [[DECsystem-10]] models, running [[TOPS-10]]. | ||
| + | |||
| + | [[Image:KA10 mod end.jpg|150px|thumb|left|B-series FLIP CHIP used in the KA10 CPU]] | ||
| − | + | It was also the machine on which the [[Incompatible Timesharing System|ITS]] and [[TENEX]] [[operating system]]s were developed, after the machines were modified to provide [[virtual memory|paging]]. | |
| − | + | ==See also== | |
| − | [[ | + | * [[KI10]] |
| + | * [[KL10]] | ||
| + | * [[KS10]] | ||
| + | |||
| + | ==External links== | ||
| − | + | * [http://www.bitsavers.org/pdf/dec/pdp10/KA10/ BitSavers KA10 documents] | |
| + | * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V1_Oct74.pdf PDP-10 module schematics Vol.1] | ||
| + | * [http://www.bitsavers.org/pdf/dec/modules/KI10_moduleSchems_V2_Oct74.pdf PDP-10 module schematics Vol.2] | ||
[[Category: PDP-10 Processors]] | [[Category: PDP-10 Processors]] | ||
Latest revision as of 06:28, 6 September 2023
| KA10 | |
 KA10-based PDP-10 system | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year Design Started: | January, 1966 |
| Year First Shipped: | September, 1967 |
| Form Factor: | mainframe |
| Word Size: | 36 bits |
| Logic Type: | silicon transistors and diodes |
| Design Type: | asynchronous with hardware subroutines |
| Instruction Speed: | 3 μsec (approximately - different instructions take different amounts of time, the CPU is not synchronous) |
| Memory Speed: | 1.0 μsec (fast), 1.8 μsec (slow) |
| Physical Address Size: | 18 bits (normal), 19/20 (ITS paging box), ?? (TENEX paging box) |
| Virtual Address Size: | 18 bits |
| Memory Management: | dual base and bounds register pairs (non-customized machines) |
| Operating System: | Monitor, ITS, WAITS, TENEX |
| Predecessor(s): | PDP-6 |
| Successor(s): | KI10 |
| Price: | US$150K (CPU), US$300-700K (system) |
The KA10 was the first generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of discrete transistors, on short single FLIP CHIP cards, plugged into large custom-wired backplanes.
It had hardware support for time-sharing (two modes, 'User' and 'Executive'), as well as base and bounds memory management hardware. These were used in the first DECsystem-10 models, running TOPS-10.
It was also the machine on which the ITS and TENEX operating systems were developed, after the machines were modified to provide paging.
