RH11 MASSBUS controller

The RH11 MASSBUS controller (generally the RH11-AB model) allowed the interconnection of MASSBUS devices such as the RP04 to systems with a UNIBUS, primarily on PDP-11's.

There is an RH11-B model; it uses the M9725-YA card; the difference is not known, but involves the two added one-shots in the lower left corner of drawing BCTB.

Second UNIBUS

The RH11 contains connectors and circuitry for two separate UNIBUSes; the second UNIBUS is primarily used on systems with multi-port memory, such as the PDP-11/45.

The registers in the RH11 are only accesssible from the 'first' UNIBUS (UNIBUS 'A'); likewise, interrupts of the CPU are only possible via UNIBUS 'A'. The RH11 can be set under software control to do DMA data transfers on either the first or second UNIBUS (UNIBUS 'B').

If no CPU is connected to UNIBUS 'B', an M9300 terminator at the start of the bus can be configured to do NPR bus grants. A jumper allows the RH11 to do block transfers on UNIBUS 'B' without going through an arbitration cycle; the 'A' UNIBUS has a mode where it can do two DMA cycles per grant.

18-bit mode

The RH11 has the capability to operate in 18-bit mode; in this mode, the PA and PB UNIBUS parity lines are used for data bits 16 and 17. The PDP-15 and KS10 made use of this capability, the latter with the RH11-C model.

(The difference between the -AB and -C is currently unknown; the latter used the M7294-YA instead of the M7294 as in the former. Since that card is the MASSBUS data buffer and control, it's likely related to the data transfer.)

Note that 18-bit mode is only available on the 'B' UNIBUS (which must be selected) if a jumper is removed; see Section 4.16 "Logic Diagram DBCE", pg. 4-28 (65 of the PDF) in the "RH11-AB Option Description" for details.

Registers

The RH11 contains 4 registers, plus a share of a fifth; they are

• RHCS1 - Control and Status 1 (shared)
• RHWC - Word Count
• RHBA - Bus Address
• RHCS2 - Control and Status 2
• RHDB - Data Buffer (for maintenance)

As is standard for the MASSBUS, all the other device registers are in the device.

Hardware

The RH11 consisted of a double system unit backplane (below) into which plugged a number of cards:

Two of them hex-sized:

• M7294 - DBC - Data Buffer and Control
• M7295 - BCT - Bus Control

Two dual-sized cards containing controller logic:

• M7296 - CSR - Control and Status
• M7297 - PAC - Parity Generation and Checking

Three dual-height M5904 MASSBUS transceiver modules.

Optionally one or two single-height cards:

• M688 - UNIBUS Power Fail Driver

The RH11 backplane also contained three SPC slots in otherwise-unused slots; they are on UNIBUS 'A'. The NPG bus grant line is routed through those slots, so they are fully capable.

Backplane layout

Board locations (as seen from the board insertion side of the backplane, not the wire-wrap pin side, as is common in DEC documentation) are:

	Connector
Slot	A	B	C	D	E	F
1	UNIBUS A In		M7297 Parity		M7296 Control/Status
2	M7295 Bus Control
3	M7294 Data/Buffer Control
4	Unused		M5904 Transceiver		M688 - UNIBUS B Power Fail	Unused
5	Unused		M5904 Transceiver		M688 - UNIBUS A Power Fail	Unused
6	Unused		M5904 Transceiver		Unused
7	UNIBUS B Out		SPC
8	UNIBUS B In		SPC
9	UNIBUS A Out		SPC

The order of the UNIBUS 'B' in/out and 'A' out slots is apparently to allow the use of an M9200 UNIBUS jumper to tie the two UNIBI together. (E.g. in the 'disk' RH11 in the KS10, where the CPU needs access to the device registers, interrupts, etc, which are on UNIBUS 'A', but also has to be connected to UNIBUS 'B', for 18-bit data transfers.)