KY11-L to CPU interface

The KY11-LA Operator's Console and the KY11-LB Programmer's Console use the same KY11 to CPU interface with all the PDP-11 CPUs which use them: the KD11-D CPU of the PDP-11/04, the KD11-E CPU of the PDP-11/34, and the KD11-EA CPU of the PDP-11/34A.

The common interface of both KY11's to the CPU allows the console to request that the CPU halt; this is done with the standard UNIBUS signal, SACK, and a pair of additional signals, Halt Request and Grant. As the names indicate, the latter two request that the main CPU halt, and allow the CPU to acknowledge that it has honoured that request. SACK is used by the console to indicate to the CPU (if asserted) that it should remain halted (with the CPU's clock inhibited), and when it should resume normal execution of instructions.

The use of SACK to keep the CPU halted means that if a system has an M9302 UNIBUS terminator, and a break in a bus grant line (e.g. from a missing grant continuity card), the machine will irretrievably 'freeze'; see UNIBUS and QBUS termination for an explanation.

Parenthetically, a HALT instruction also uses this mechanism; decoding of one (by the instruction decoding PROMs) asserts Halt Request directly - there is no microcode to implement the HALT instruction. When the console ceases to assert SACK, that allows the CPU clock to resume operation, and thus the execution of instructions.

The physical connection from the KY11 to the CPU differs slightly between the KY11-LA and the KY11-LB (all 3 CPUs are identical in how they connect). For the LY11-LA, a flat cable runs directly from the console to the CPU. For the KY11-LB, a flat cable runs from the console to the M7859 board, which plugs into the MUD backplane holding the CPU (the special DD11-P backplane for the two -11/34's, and either a DD11-P or either the DD11-C or DD11-D backplanes for the -11/04). The M7859 communicates with the CPU over that backplane.

Documentation

The KY11 to CPU interface is documented in a number of diverse locations.

KY11-LB

In EK-KY1LB-MM, see:

• 5.3.15 "Halt Logic"

KD11-D

In EK-KD11D-TM, see:

• 5.5.3.5 "Operate Instructions"
  • "Halt Instructions - Enable HLT RQST L"
• 5.9 "Processor Clock"
  • "It is turned off ... 7. While BUS SACK is asserted"
• 5.10.3 "Halt Grant Request"

KD11-E

In EK-KD11E-TM, see:

• 4.5.3.5 "Operate Instructions"
  • "HALT - Enable HLT RQST L"
• 4.9 "Processor Clock"
  • "The clock is turned off ... 9. After a Halt instruction is executed"
• 4.10.3 "Halt Grant Requests"

KD11-EA

In EK-KD1EA-MM, see:

• 4.5.3.5 "Operate Instructions"
  • "HALT - Enable HLT RQST L"
• 4.9 "Processor Clock"
  • "The clock is turned off ... 9. After a Halt instruction is executed"
• 4.10.3 "Halt Grant Requests"
  • "The user can maintain the processor in this inactive state (Halted) indefinitely. When the HALT switch is released, the user's console releases BUS SACK L, and the processor continues operation"

This text is obviously for the KY11-LA; the KY11-LB will operate identically: when the console releases SACK (e.g. after 'Continue' is entered), the processor resumes operation.

See also

• M8264 No-SACK Timeout Module
• UNIBUS and QBUS termination - in particular, the SACK turnaround and CPU hangs section

External links

• KY11-LB programmer's console/interface module operation and maintenance manual (EK-KY1LB-MM-001)
• KD11-D Processor Manual (PDP-11/04) (EK-KD11D-TM-PRE)
• KD11-E central processor maintenance manual (EK-KD11E-TM-001)
• KD11-EA central processor maintenance manual (EK-KD1EA-MM-001)