Difference between revisions of "KS10"
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Revision as of 00:21, 20 October 2017
| KS10 | |
| Manufacturer: | Digital Equipment Corporation |
|---|---|
| Architecture: | PDP-10 |
| Year First Shipped: | 1978 |
| Form Factor: | small mainframe |
| Word Size: | 36 bits |
| Logic Type: | LS TTL ICs |
| Design Type: | clocked synchronous microcoded |
| Clock Speed: | 20 MHz |
| Physical Address Size: | 19 bits (some had 20) |
| Virtual Address Size: | 18 bits |
| Memory Management: | paging, 512-word pages |
| Operating System: | TOPS-10, TOPS-20, ITS |
| Predecessor(s): | KL10 |
| Successor(s): | None |
The KS10 was the fourth and last generation of PDP-10 processors (themselves, exact re-implementations of the earlier PDP-6 architecture). It was built out of LS TTL chips, along with AMD 2901 bit slice chips, on four super hex cards.
