KL10

KL10
Manufacturer:	Digital Equipment Corporation
Architecture:	PDP-10
Year Design Started:	January, 1972
Year First Shipped:	June, 1975
Form Factor:	mainframe
Word Size:	36 bits
Logic Type:	ECL ICs
Design Type:	clocked synchronous, microcoded
Microword Width:	75 (Model A) 76 (Model B)
Microcode Length:	1280 (Model A) 2K (Model B)
Clock Speed:	500 nsec
Cache Size:	2K words
Memory Speed:	1.0 μsec (initial core memory), 500 nsec (later MOS main memory)
Physical Address Size:	22 bits
Virtual Address Size:	18 bits (Model A and B) 23 bits (Model E)
Memory Management:	paging, 512-word pages
Operating System:	TOPS-10, TOPS-20, ITS, WAITS, TENEX, TYMCOM-X
Predecessor(s):	KI10
Successor(s):	none
Price:	US$250K (CPU), US$600K-1.2M (system)

The KL10 was the third generation of PDP-10 processors. It was built out of ECL, on hex cards. It was the first microprogrammed PDP-10 processor; the design was inspired by Stanford's Superfoonly.

The CPU had two main units, the 'E Box' ('Execution') and the 'M Box' ('Memory'). It provided three types of busses to the rest of the components of the system; the 'E Bus', from the E Box; and the 'S Bus' ('Storage'), and later the 'C Bus' ('Channel'), from the M Box. The S Bus was for the attachment of main memory units (it was later upgraded to something called the 'X Bus'), while the C Bus allowed DMA accesss to main memory.

Up to 4 DTE20 Interfaces (which allowed connection of a PDP-11 front end), and up to 8 RH20 MASSBUS controllers could be connected to the E Bus (the latter were also connected to the C Bus). At least one PDP-11, the 'master', was required; it could bootstrap the KL10, including loading the microcode.

A DMA20 Memory Bus Controller could be attached to the S Bus, to provide an external memory bus (compatible with the earlier KA10 and KI10). Similarly, an DIA20 In/Out Bus Controller could be attached to the E Bus, to provide a KA10/KI10 compatible I/O bus.

The KL10 was used in the DECsystem-10 models 108x and 109x systems (initially with an external memory bus), and in the high-end 20xx systems of the DECSYSTEM-20 line (with an internal memory bus).

Like its predecessor, the KI10, it was initially released in a single-processor version; a two-CPU version was released later.

Versions

There were a number of variants over the lifetime of the KL10; the situation is confusing because there appear to be three different, somewhat orthogonal, namespaces for KL10 Variants:

• CPU hardware variants (PA and PV);
• informal internal names for CPU variations ('Model A' and 'Model B');
• KL10 'models' (-A through -E).

The later KL10-PV supported the 'Extended' PDP-10 architecture, with support for multiple 'sections' (256K-word address spaces), available to both the kernel and the user (although apparently only TOPS-20 supported the latter). The earlier machines could be field upgraded to a -PV, but it apparently needed a new backplane.

There is currently a lack of clarity aout the MCA25 KL Cache/Paging Upgrade, which increased the size of both the main memory cache, and the paging cache, as well as improved the functionality of the latter. Some sources indicate that it too required a new backplane, becoming the 'Model C'.

As far as is known, 'Model A' is an internal aphorism for -PA, and 'Model B' for -PV; the two are described in a DEC document as:

• "KL10-PA - A basic ECL processor with slots for cache and internal channels. Unofficially .. referred to as the Model A machine."
• "KL10-PV - A KL10-PA which has been modified to include extended addressing, more extensive microcode, and a faster clock. Unofficially .. referred to as the Model B machine."

Many of the 'models' (e.g. 'KL10-C' and 'KL10-D') appear to be names for particular configurations (with various options, such as the DMA20 and DIA20); here is a DEC table which (hopefully authoritatively) defines them:

Model	PV	Cache	Int Chans	Max DTEs	Max RH20s	DIA	DMA
KL10-A	No	Yes	No	1	0	Yes	Yes
KL10-B	No	Yes	Yes	4	8	Yes	Yes
KL10-C	No	Optional	Yes	4	8	No	No
KL10-D	Yes	Yes	Yes	4	8	Yes	Yes
KL10-E	Yes	Optional	Yes	4	8	*	No

(The meaning of the '*' is not clear.)

The 'KL10-R' appears to be a Model E in a new cabinet design, one compliant with newer FCC RFI emissions standards, but it may also refer to systems with the MCA25.

Note that the early KL10-A only supported a single DTE20, and no RH20s, and it was the later KL10-B and up, the first two also with the Model A CPU, which supported up to 4 DTE20s and up to 8 RH20s. This is because the E Box and M Box were both on the main CPU backplane, but I/O functionality was relegated to backplanes in the second bay of the CPU. These differed in the KL10-B and up, to support the larger I/O configuration.

One significant division between KL-based systems is between those with an external memory bus, and those with an internal memory bus (the native S Bus).

The DEC numeric model numbers - a fourth namespace - are even more confused, since a 1090 could be either a "KL10-B(PA) or KL10-D(PV)"; similarly, the 2040 and 2050 could be a "KL10-C(PA) or KL10-E(PV)".

Well-known KL10's

There was a single KL10 ITS machine, MIT-MC. It was later renamed to MX after a KS10 took the 'MC' identity, and was finally shut down in 1988; it is now in storage at the Living Computers Museum. There was also a KL10 in the SAIL WAITS system.

External Links

• Digital's DECSYSTEM-20 - Part 5 - CPU (KL10)