KD11-K CPU

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Revision as of 22:51, 11 January 2022 by Jnc (talk | contribs) (two UNIBUS connectors)
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The KD11-K was the CPU of the PDP-11/60. It provided the subset PDP-11 memory management, and used a UNIBUS for its main memory access (although a built-in cache was standard).

It provided the full FP11 floating point using microcode; as an option, the FP11-E Floating Point Processor, a 4 hex board co-processor which provided a high-performance implementation, was also available. Also available were either a User Control Store (1KW of read-write microcode), an Extended Control Store (ROM microcode), or a Diagnostic Control Store.

One unusual aspect was that the CPU's backplane had a separate UNIBUS connectors for I/O activity, and for memory access. The FMPS indicates (pg. 4) that devices that do interupts and DMA must be connected to the I/O UNIBUS, and not to the memory UNIBUS; but it also indicates (pg. 3) that there is only a single UNIBUS. (Perhaps all the bus grant lines from the bus arbitration circuitry in the CPU are only connected to the I/O connector?)

Microcode

It was a microcoded CPU, using 48-bit wide micro-words; the address space of the micro-engine was 212 words, divided into 8 blocks. The allocation of the blocks was:

  1. Base instructions
  1. Console and Error log
  2. EIS, Initialization
  3. Floating point
  4. Floating point
  5. ECS
  6. ECS/UCS
  7. ECS/UCS

Implementation

It consisted of a custom 14-slot backplane ((DEC part number 70-12953), and 6 hex boards:

  • uWord (M7872)
  • Decode (M7873)
  • Data Path (M7874)
  • KT/Cache (M7875)
  • Timing (M7876)
  • Status (M7827)

for the basic CPU. They were held in slots 2-7 of the backplane:

Connector
Slot A B C D E F
1 WCS or ECS or DCS (optional)
2 uWord (M7872)
3 Decode (M7873)
4 Data Path (M7874)
5 KT/Cache (M7875)
6 Timing (M7876)
7 Status (M7827)
8 Floating Point Next Micro-Address (M7878)
9 Floating Point Exponent (M7879)
10 Multiplying Network (M7880)
11 Floating Point ALU (M7881)
12 Unused SPC
13 Bootstrap SPC
14 UNIBUS Out SPC

The optional FPP used slots 8-11 of the backplane; a single slot, slot 1, held the microcode option. The remaining slots in the backplane, 12-14, were SPC slots.

External links