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• TOPS-10
  ...nded from the 'Monitor' OS used on the [[PDP-6]]. It provided both [[batch processing]] and [[time-sharing]] capabilities. TOPS-10 allowed programs to be separated into data and [[object code]] segments; the latter could be shared by all [[process]]
  1 KB (190 words) - 03:32, 28 November 2023
• RH11 MASSBUS controller
  ...1 can be set under [[software]] control to do [[Direct Memory Access|DMA]] data transfers on either the first or second UNIBUS (UNIBUS 'B'). ...t mode]]; in this mode, the PA and PB UNIBUS [[parity]] lines are used for data bits 16 and 17. The [[PDP-15]] and [[KS10]] made use of this capability, th
  6 KB (951 words) - 15:40, 25 February 2022
• KS10
  ...he main [[backplane]]), to which are attached the [[microcode]]d [[Central Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] ada ...internal bus; the address is transferred on one cycle, and the associated data on a following cycle.
  8 KB (1,237 words) - 19:48, 14 July 2023
• PDP-15
  ...between protected and un-protected memory, and two modes for the [[Central Processing Unit|CPU]]. A memory relocation option, the KT15, with a [[base and bounds] ...r 18-bit mode]], where the two [[parity]] lines were recycled into 2 extra data lines.
  4 KB (591 words) - 13:40, 11 July 2023
• RH70 MASSBUS controller
  ...[[interrupt]]s, and access to the device's [[register]]s by the [[Central Processing Unit|CPU]]). ...connection to the cache is purely for data transfer control purposes; all data reads and writes go directly to the actual main memory (although the RH70's
  2 KB (318 words) - 15:45, 25 February 2022
• Program
  * direction to move data from one place to another ...loaded into the [[main memory]] of the computer, from where the [[Central Processing Unit|CPU]] will fetch the individual [[instruction]]s of the program, and e
  1 KB (201 words) - 11:55, 4 December 2023
• PDP-9
  | caption = PDP-9 at MIT Cognitive Information Processing Group ...nt Corporation|DEC]]'s fourth 18-bit computer, and the first DEC [[Central Processing Unit|CPU]] to use [[microcode]]. A little over 400 were built. It was basic
  6 KB (801 words) - 22:14, 9 February 2024
• IBM 709
  ...ddress]]ing, and [[channel]]s (called 'Data Synchronizers' at the time). A Data Synchronizer had two channels, to each of which could be attached a [[card ...ww-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP709.html 709 Data Processing System] - IBM Archive page
  2 KB (304 words) - 02:19, 9 August 2022
• IBM 7090
  It was designed hurriedly to meet the requirements of Sylvania, the data processing subcontractor for the [[BMEWS]] missile warning [[radar]] network, which wa ...-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7090.html 7090 Data Processing System] - IBM Archive page
  2 KB (287 words) - 02:18, 9 August 2022
• IBM 7094
  ...-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP7094.html 7094 Data Processing System] - IBM Archive page
  2 KB (269 words) - 02:16, 9 August 2022
• KK11-A Cache Memory
  ...e [[KD11-EA CPU]], one which added a high-speed [[cache]] to the [[Central Processing Unit|CPU]]. Each cache entry was 28 bits wide, containing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] addr
  4 KB (553 words) - 02:36, 12 October 2022
• UNICHANNEL 15 System
  ...acts as an I/O [[front end]], partially to offload the PDP-15's [[Central Processing Unit|CPU]], but also to allow PDP-15 systems access to devices which did no * A data channel between the two CPUs, which allows them to interrupt each other; th
  1 KB (180 words) - 14:48, 28 November 2022
• MX15-B Memory Multiplexer
  The MX15-B allowed the PDP-11 (both the [[Central Processing Unit|CPU]], and [[Direct Memory Access|DMA]] devices on the PDP-11's [[UNIB ...ers]] over it; they used the two UNIBUS [[parity]] lines for the two extra data bits of the 18-bit PDP-15. The two extra bits were not used by the PDP-11 o
  2 KB (314 words) - 00:35, 1 December 2022
• M9312 ROM
  ...]] emulator over the console [[asynchronous serial line]], basic [[Central Processing Unit|CPU]] and [[main memory]] diagnostics, and the ability to [[bootstrap] The board used five 4-bit wide PROMs to hold the data; the DEC-supplied pre-programmed PROMs included the console emulator and di
  7 KB (1,103 words) - 11:42, 3 April 2022
• KD11-A CPU
  The '''KD11-A''' [[PDP-11]] [[Central Processing Unit|CPU]] for the [[PDP-11/35]] and [[PDP-11/40]] was a multi-board [[micr * M7231 - Data Paths
  4 KB (588 words) - 05:52, 8 April 2024
• Able ENABLE
  The ENABLE took an incoming UNIBUS segment, containing the [[Central Processing Unit|CPU]] and all [[Direct Memory Access|DMA]] [[peripheral controller|dev ...rt [[PDP-11 Memory Management|Split I+D]], whether it is an instruction or data fetch.
  9 KB (1,569 words) - 15:47, 6 February 2024
• DL10 PDP-11 Data Link
  The '''DL10 PDP-11 Data Link''' connects [[PDP-10]] [[mainframe]]s to [[PDP-11]]s used as communica ...]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connected to [[KA10]]s and [[KI10]]s, b
  5 KB (664 words) - 17:27, 7 November 2023
• TM10 Magnetic Tape Control
  ...F10 Data Channel]] for data transfers, to reduce the load on the [[Central Processing Unit|CPU]].
  1 KB (221 words) - 22:18, 21 April 2024
• Rubin 10-11 interface
  ...s) did not have access to the KA10's memory (unlike with the [[DL10 PDP-11 Data Link|DL10]] and [[DTE20 Ten-Eleven Interface|DTE20]], similar devices). ...particular alignment of the window on the UNIBUS side was necessary; the [[data path]] for the [[address]] must have contained an [[adder]].)
  3 KB (402 words) - 17:01, 22 March 2024
• PDP-5
  ...boards (equal to the [[word]] length of the machine) formed the [[Central Processing Unit|CPU]]. To minimize the initial basic cost, it had an [[input/output|I/ ...data.computerhistory.org/brochures/dec.pdp-5.1964.102646094.pdf Programmed Data Processor-5] - marketing brochure from DEC
  2 KB (360 words) - 20:03, 7 February 2024

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