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  • ...visible to to user as first-class objects, are supported in the [[Central Processing Unit|CPU]] (in the [[instruction]]s), etc; whereas pages are generally invi ...t size, measured in small units, is often stored in a field as part of the data which describes the segment to the CPU's hardware), whereas with variable p
    5 KB (876 words) - 20:01, 22 January 2024
  • The '''KA11''' is the [[Central Processing Unit|CPU]] of the [[PDP-11/20]], the first [[PDP-11]]. It was the only PDP- * [[Data path|Data Paths]]
    9 KB (1,356 words) - 23:10, 29 February 2024
  • ...[[register]] names must be known, as well as the function of the [[Central Processing Unit|CPU]] and [[peripheral|device]] [[UNIBUS]]es, and also high-level inte [[Image:KT11-B_DataPaths.jpeg|450px|right|Main data paths]]
    31 KB (4,983 words) - 18:22, 2 July 2023
  • There are several single-board [[PDP-11]] [[Central Processing Unit|CPUs]] which all use the 'Jaws' [[J-11 chipset]]: ...even if that memory location is faulty - the CPU is getting the (correct) data from the cache.
    3 KB (457 words) - 14:32, 21 February 2023
  • ...P-11 architecture]]. It was used in the [[KDF11 CPUs]]. The main [[Central Processing Unit|CPU]] was implemented in two [[integrated circuit|chips]] (carried on ...although the KEF11-A is [[microcode]], there are enough pins for both the data [[bus]], and the microcode bus.)
    2 KB (384 words) - 23:50, 28 March 2022
  • The '''Central Processing Unit''', usually abbreviated as '''CPU''', or simply called a '''processor' Instructions include data-handling instructions (such as arithmetic and logical operations), and cont
    1 KB (196 words) - 13:14, 5 November 2023
  • ...ion (the 'Control Bus'), and a [[synchronous]] data transfer section (the 'Data Bus'). The two sections operate completely independently. ...sing Unit|CPU]] access to device registers implemented in the devices. The data section is 18 (optionally 16) bits wide, to allow use with both DEC's 36-bi
    5 KB (729 words) - 21:36, 2 December 2023
  • Instructions in the LINC [[Central Processing Unit|CPU]] could seek to a given block, and then read or write multiple blo The tape contained timing and mark tracks along with three data tracks; the first two allowed not only the ability to re-write individual b
    3 KB (519 words) - 02:13, 28 February 2024
  • ...a [[Direct Memory Access|DMA]] peripheral to the PDP-8, using the PDP-8 [[data break]] mechanism). A combined [[front panel]] allowed control of both CPUs
    2 KB (328 words) - 13:46, 11 July 2023
  • ...ch uses tiny rings of magnetic material ('cores', hence the name) to store data; magnetized in one direction, such a core represents a '1' [[bit]], and in ...location in main memory, the location can be read out, with the [[Central Processing Unit|CPU]] telling the memory to wait before the write-back, so the CPU can
    8 KB (1,299 words) - 02:33, 4 March 2024
  • '''Main memory''' refers to the [[memory]] from which the [[Central Processing Unit|CPU]] reads its [[instruction]]s as it [[execute]]s them; typically, a ...ata for immediate access by the CPU. Computers which keep instructions and data in the same memory are called 'von Neumann' [[architecture]]s; those which
    2 KB (250 words) - 17:10, 11 September 2019
  • ...erface boards (an M8158 address buffer board, and either an M8159 or M8164 data buffer board; the M8159 could only be used with 64KB memory modules, wherea [[Image:M8159MK11DBuf.jpg|thumb|250px|right|M8159 Data Buffer card (also with memory bus terminators)]]
    8 KB (1,276 words) - 03:23, 6 February 2024
  • As with the FP11 version, it was tightly integrated with the [[Central Processing Unit|CPU]], so that the CPU processed a mix of 'regular' and floating point ...e|regular PDP-11 registers]] as a pointer to load and store floating point data from/to memory; floating point values could only be stored in [[main memory
    2 KB (355 words) - 17:49, 7 December 2021
  • ...the functionality needed to control the internal operation of a [[Central Processing Unit|CPU]]. ...f the CPU's internal [[hardware]] elements during that microcycle: routing data out of [[register]]s (including internal registers not visible to the progr
    6 KB (853 words) - 14:25, 22 January 2024
  • ...uad]] board, the M7239, which plugs into a pre-wired slot in the [[Central Processing Unit|CPU]] [[backplane]]. ...but it also uses microcode stored on the KE11-E, to control registers and data paths elsewhere.
    2 KB (246 words) - 02:34, 12 October 2022
  • | DPR || OVR || FRM || PAR || colspan=4 | Line || colspan=8 | Data ...to the DH11 with a pair of BC08S cables, which carried the 'main' signals (data, etc - i.e. non-modem control); these cables were thus required for both 'l
    10 KB (1,443 words) - 02:27, 19 February 2023
  • ...here; they are for a [[peripheral|device]] to gain control of the UNIBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. ...name comes from the fact that the device cannot request that the [[Central Processing Unit|CPU]] perform any action (i.e. an [[interrupt]]) while the device has
    1 KB (212 words) - 18:50, 6 July 2022
  • ...Processing Unit|CPU]], using [[instruction]]s performed by the CPU to move data - as opposed to [[Direct Memory Access|DMA]], in which the [[peripheral|dev ...', in which the CPU has to regularly check the device to see if it needs a data transfer, and ii) '''interrupt-driven''', where the device causes an [[inte
    1 KB (192 words) - 23:12, 20 October 2021
  • [[Image:KD11-E M7265.jpg|250px|right|thumb|M7265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M7265''' Data Paths module and the '''M7266''' Control module. They plugged into a modifi
    5 KB (791 words) - 02:23, 6 December 2022
  • [[Image:KD11-EA M8265.jpg|250px|right|thumb|M8265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M8265''' Data Paths module and the '''M8266''' Control module.
    6 KB (1,045 words) - 22:47, 31 March 2022

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