Search results

Create the page "Data processing" on this wiki! See also the search results found.

• Main memory
  '''Main memory''' refers to the [[memory]] from which the [[Central Processing Unit|CPU]] reads its [[instruction]]s as it [[execute]]s them; typically, a ...ata for immediate access by the CPU. Computers which keep instructions and data in the same memory are called 'von Neumann' [[architecture]]s; those which
  2 KB (250 words) - 17:10, 11 September 2019
• MK11 memory system
  ...erface boards (an M8158 address buffer board, and either an M8159 or M8164 data buffer board; the M8159 could only be used with 64KB memory modules, wherea [[Image:M8159MK11DBuf.jpg|thumb|250px|right|M8159 Data Buffer card (also with memory bus terminators)]]
  8 KB (1,276 words) - 03:23, 6 February 2024
• FIS floating point
  As with the FP11 version, it was tightly integrated with the [[Central Processing Unit|CPU]], so that the CPU processed a mix of 'regular' and floating point ...e|regular PDP-11 registers]] as a pointer to load and store floating point data from/to memory; floating point values could only be stored in [[main memory
  2 KB (355 words) - 17:49, 7 December 2021
• Microcode
  ...the functionality needed to control the internal operation of a [[Central Processing Unit|CPU]]. ...f the CPU's internal [[hardware]] elements during that microcycle: routing data out of [[register]]s (including internal registers not visible to the progr
  6 KB (853 words) - 14:25, 22 January 2024
• KE11-F Floating Instruction Set
  ...uad]] board, the M7239, which plugs into a pre-wired slot in the [[Central Processing Unit|CPU]] [[backplane]]. ...but it also uses microcode stored on the KE11-E, to control registers and data paths elsewhere.
  2 KB (246 words) - 02:34, 12 October 2022
• DH11 asynchronous serial line interface
  | DPR || OVR || FRM || PAR || colspan=4 | Line || colspan=8 | Data ...to the DH11 with a pair of BC08S cables, which carried the 'main' signals (data, etc - i.e. non-modem control); these cables were thus required for both 'l
  10 KB (1,443 words) - 02:27, 19 February 2023
• Non-Processor Request and Grant
  ...here; they are for a [[peripheral|device]] to gain control of the UNIBUS's data section so that it may perform a [[Direct Memory Access|DMA]] cycle. ...name comes from the fact that the device cannot request that the [[Central Processing Unit|CPU]] perform any action (i.e. an [[interrupt]]) while the device has
  1 KB (212 words) - 18:50, 6 July 2022
• Programmed I/O
  ...Processing Unit|CPU]], using [[instruction]]s performed by the CPU to move data - as opposed to [[Direct Memory Access|DMA]], in which the [[peripheral|dev ...', in which the CPU has to regularly check the device to see if it needs a data transfer, and ii) '''interrupt-driven''', where the device causes an [[inte
  1 KB (192 words) - 23:12, 20 October 2021
• KD11-E CPU
  [[Image:KD11-E M7265.jpg|250px|right|thumb|M7265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M7265''' Data Paths module and the '''M7266''' Control module. They plugged into a modifi
  5 KB (791 words) - 02:23, 6 December 2022
• KD11-EA CPU
  [[Image:KD11-EA M8265.jpg|250px|right|thumb|M8265 Data Paths card]] ...o [[DEC card form factor|hex]] [[printed circuit board]]s, the '''M8265''' Data Paths module and the '''M8266''' Control module.
  6 KB (1,045 words) - 22:47, 31 March 2022
• Cache
  ...a larger collection of data, implemented in such a way that access to the data copy in the cache is faster than to that in the large, full store. ...d disk blocks are kept in main memory, and network caches, where copies of data read from the network are kept on the local machine's disk.
  1 KB (251 words) - 00:58, 17 May 2023
• NORD-TSS
  ...ing the summer holidays of 1971, Bo Lewendal (system programmer at [[Norsk Data]]) implemented the initial version. It was further developed throughout 197 * Has a [[batch processing]] system
  1 KB (181 words) - 15:15, 9 September 2022
• VAXstation II
  {{InfoboxVAX-Data ...de); and the QBUS only for its [[input/output|I/O]] [[bus]]. Its [[Central Processing Unit|CPU]] was the [[MicroVAX II]]; the [[VCB01 Video Controller]] provided
  2 KB (254 words) - 16:59, 15 January 2024
• VAX 6000 Model 400
  {{InfoboxVAX-Data ...ange member of the [[VAX 6000 series]] line, the first to provide [[vector processing]].
  2 KB (153 words) - 18:26, 20 May 2024
• VAX 8300
  {{InfoboxVAX-Data The '''VAX 8200''' is a mid-range [[VAX]] dual-[[Central Processing Unit|CPU]] [[multi-processor]] system built around the [[VAX Bus Interconne
  2 KB (287 words) - 14:43, 19 May 2024
• VAX 8350
  {{InfoboxVAX-Data ...s an improved version of the [[VAX 8300]] mid-range [[VAX]] dual-[[Central Processing Unit|CPU]] [[multi-processor]] system, built around the [[VAX Bus Interconn
  2 KB (248 words) - 14:49, 19 May 2024
• VAX 8700
  {{InfoboxVAX-Data The '''VAX 8700''' is a single-[[Central Processing Unit|CPU]] version of the [[VAX 8800]].
  2 KB (192 words) - 00:28, 21 May 2024
• VAX 8800
  {{InfoboxVAX-Data The '''VAX 8800''' is a dual-[[Central Processing Unit|CPU]] version of the [[VAX 8700]].
  2 KB (237 words) - 00:30, 21 May 2024
• VAX 88x0
  {{InfoboxVAX-Data ...computer models, the difference between them being the number of [[Central Processing Unit|CPUs]] installed in the basic cabinet:
  2 KB (206 words) - 00:24, 21 May 2024
• VAXstation 3520/3540
  {{InfoboxVAX-Data ...around a unique [[bus]], the [[M-bus]], to which is attached the [[Central Processing Unit|CPU]], [[main memory]], a [[graphics]] adaptor, and an [[input/output|
  3 KB (298 words) - 06:49, 17 April 2024

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)