KD11-K CPU

The KD11-K was the CPU of the PDP-11/60. It provided the subset PDP-11 memory management, and used the UNIBUS for its main memory access (although a built-in cache was standard).

It provided the full FP11 floating point using microcode; as an option, the FP11-E Floating Point Processor, a 4 hex board co-processor which provided a high-performance implementation, was also available. Also available were either a User Control Store (1KW of read-write microcode), an Extended Control Store (ROM microcode), or a Diagnostic Control Store.

Microcode

It was a microcoded CPU, using 48-bit wide micro-words; the address space of the micro-engine was 2¹² words, divided into 8 blocks. The allocation of the blocks was:

0. Base instructions

1. Console and Error log
2. EIS, Initialization
3. Floating point
4. Floating point
5. ECS
6. ECS/UCS
7. ECS/UCS

Implementation

It consisted of a custom 14-slot backplane, and 6 hex boards:

• uWord (M7872)
• Decode (M7873)
• Data Path (M7874)
• KT/Cache (M7875)
• Timing (M7876)
• Status (M7827)

for the basic CPU. They were held in slots 2-7 of the backplane:

	Connector
Slot	A	B	C	D	E	F
1	WCS/ECS/DCS (optional)
2	uWord (M7872)
3	Decode (M7873)
4	Data Path (M7874)
5	KT/Cache (M7875)
6	Timing (M7876)
7	Status (M7827)
8	Floating Point Next Micro-Address (M7878)
9	Floating Point Exponent (M7879)
10	Multiplying Network (M7880)
11	Floating Point ALU (M7881)
12	Unused		SPC
13	Bootstrap		SPC
14	UNIBUS Out		SPC

The optional FPP used slots 8-11 of the backplane; a single slot, slot 1, held the microcode option. The remaining slots in the backplane, 12-14, were SPC slots.

External links

• PDP-11/60 - BitSavers
  • KD11K Processor (11/60) Technical Description Manual - Maintenance Features (EK-KD11K-TD-PRE)
  • 11/60 Microprogramming Specification
  • 11/60 Basic Field Maintenance Print Set (MP00409)
  • KU116-AA Field Maintenance Print Set (MP00500)