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• Direct Access Storage Device
  ...'''DASD''', is [[International Business Machines|IBM]] jargon for [[random access]] [[secondary storage]] devices, such as [[floppy disk]]s, hard [[disk]]s,
  277 bytes (37 words) - 14:50, 25 August 2021
• Random Access Memory
  '''Random Access Memory''' (often given as '''RAM''') is slang term for a computer's [[main ...disk]] [[secondary storage]] (although technically disks are also [[random access]] - unlike, say, [[magnetic tape]] secondary storage).
  457 bytes (64 words) - 13:25, 20 November 2023
• Direct Memory Access
  '''Direct Memory Access''', usually abbreviated as '''DMA''', refers to a now-very-common technique ...e. In the second, the memory has multiple ports, and the device has direct access to the memory via one of the ports.
  751 bytes (125 words) - 23:08, 20 October 2021
• Random access memory
  #Redirect [[Random Access Memory]]
  34 bytes (4 words) - 05:21, 12 November 2016
• Carrier-Sense Multiple Access with Collision Detection
  ...ion''' (often given as the acronym, '''CSMA-CD''') is a way of controlling access to a [[Local area network|LAN]] using a [[broadcast]] bus (i.e. a shared br
  1 KB (181 words) - 16:10, 7 June 2022
• Direct memory access
  #Redirect [[Direct Memory Access]]
  34 bytes (4 words) - 16:43, 14 May 2018
• Access time
  ...etimes '''response time''') is the time period between the start of a read access cycle, and the point in time when the data is returned to the requestor. ...n the request arrives, that can delay the memory's response - and thus the access time for that particular cycle.
  690 bytes (113 words) - 02:11, 20 September 2022
• Random access
  ...go to disparate [[address]]es without significant delays; in '''sequential access''' memories, only successive operations to following locations can be done
  834 bytes (110 words) - 01:56, 24 December 2018
• Sequential access
  #Redirect [[Random access]]
  27 bytes (3 words) - 15:52, 10 October 2018
• DRV11-B Direct Memory Access Interface
  ...[[bit]] parallel ports, one input, and one output; it uses [[Direct Memory Access|DMA]] to transfer data.
  3 KB (380 words) - 03:54, 10 June 2020
• MSV11-L MOS Random-Access Memory
  [[Access time]] is 210-230 nsec for reads, and 90-120 nsec for writes; [[cycle time]
  6 KB (926 words) - 14:10, 22 September 2022
• MSV11-P MOS Random-Access Memory
  4 KB (600 words) - 21:23, 2 July 2023
• DR11-W Direct Memory Access Interface
  ...[[parallel interface]] for the [[UNIBUS]], one which used [[Direct Memory Access|DMA]] to transfer data to a user device. It was a single [[DEC card form fa .../www.bitsavers.org/pdf/dec/unibus/EK-DR11W-UG-004.pdf DR11-W Direct Memory Access Interface Module User's Guide] (EK-DR11W-UG-004)
  5 KB (746 words) - 17:48, 2 December 2021
• Media Access Control Address
  '''Media Access Control Addresses''' (usually shortened to the acronymic form, '''MAC Addre
  1 KB (162 words) - 01:15, 11 July 2022
• Media Access Control address
  #Redirect [[Media Access Control Address]]
  42 bytes (5 words) - 01:15, 11 July 2022
• Minimum access coding
  33 bytes (3 words) - 22:14, 24 March 2024

Page text matches

• DECnet
  ...int-to-point links only. Introduction of file transfer (FAL), remote file access (DAP), task-to-task programming interfaces and network management features. ...ntroduction of adaptive routing capability, downline loading (MOP), record access, a network management architecture, and gateways to other types of networks
  17 KB (2,405 words) - 17:43, 13 January 2024
• RSTS/E
  ...ude [[DIGITAL Command Language|DCL]] as a choice for the CLI, giving users access to essentially the same command language used in [[RSX-11]] and, later, [[V
  14 KB (2,134 words) - 16:06, 3 May 2023
• PDP-11/10
  ...memory|ROM]] (1 Kword) and a small amount of [[core memory|core]] [[Random Access Memory|RAM]] (128 words). It is not clear if any of these machines were eve
  2 KB (233 words) - 19:22, 8 February 2024
• Nuclear Data
  | access-date=September 26, 2016
  2 KB (243 words) - 18:25, 13 January 2024
• QBUS
  ...and [[peripheral controller]]s through read-write cycles, [[Direct Memory Access|DMA]], and [[interrupt]]s, as well as in much of the low-level detail, such
  13 KB (2,043 words) - 23:27, 14 January 2024
• UNIBUS
  ...nd device [[register]]s; and the ability for devices to do [[Direct Memory Access|DMA]] transfers to memory, and to [[interrupt]] the CPU.
  13 KB (2,162 words) - 23:26, 14 January 2024
• PDP-11/34
  ==Register access==
  4 KB (536 words) - 19:28, 8 February 2024
• PDP-11/20
  | memory speed = [[MM11-E and MM1-F core memories|MM11-E]]: 500 nsec [[access time]]<br>&nbsp; &nbsp; &nbsp; 1.2 μsec [[cycle time]]
  6 KB (900 words) - 19:27, 31 December 2023
• PDP-11/24
  ...UNIBUS and the EUB for access to all of memory for UNIBUS [[Direct Memory Access|DMA]] devices; without it, the UNIBUS [[address space]] was statically mapp ...ath for addressing information to flow from the UNIBUS to the EUB, for DMA access to main memory by devices.
  8 KB (1,395 words) - 23:37, 29 February 2024
• PDP-11/44
  ...ut not [[address]] lines); [[Direct Memory Access|DMA]] devices could gain access to the memory via a [[UNIBUS map]] which connected the two, and mapped UNIB
  4 KB (584 words) - 23:42, 29 February 2024
• PDP-11/45
  ...em), or the -11/45's main UNIBUS (the 'A' UNIBUS), so that [[Direct Memory Access|DMA]] devices on that UNIBUS could do [[input/output|I/O]] to the fast memo
  6 KB (895 words) - 23:52, 29 February 2024
• PDP-11/70
  ...[[main memory]] via a new Main Memory Bus, and changes to the CPU to allow access to that much memory * A [[UNIBUS map]] to allow devices on the UNIBUS access to all of that memory
  5 KB (729 words) - 23:43, 29 February 2024
• RK06/07 disk drive
  | average access time = 49 msec
  3 KB (492 words) - 00:27, 15 August 2023
• RK11 disk controller
  The name of bit 6 has changed slightly from the RK11-C to the -D ("Access Ready" to "R/W/S Ready"), but it seems to be basically the same functionali
  14 KB (2,038 words) - 23:04, 13 September 2023
• RK611 disk controller
  ...dge [[disk]] [[drive]]s. All data transfers are done using [[Direct Memory Access|DMA]]. Data is protected with a [[hardware]]-generated and checked [[error-
  4 KB (563 words) - 13:33, 26 February 2023
• RS11 disk drive
  | minimum access time = 258 16 μsec | average access time = 16.9 msec (60 Hz [[alternating current|AC]] power)<br>20.3 msec (50
  1 KB (212 words) - 22:14, 14 August 2023
• RL01/02 disk drive
  | average access time = 67.5 msec Some later drives have access panels which can be removed to gain to the solenoid. On older ones, one has
  8 KB (1,357 words) - 16:33, 18 August 2023
• PDP-11 architecture
  ...ous later models added various instructions for Processor Status Word (PS) access, maintenance, etc.
  13 KB (1,949 words) - 17:37, 29 February 2024
• RK05 disk drive
  | average access time = 70 msec
  7 KB (1,170 words) - 00:30, 15 August 2023
• RK8-E disk controller
  ...05 drives. It used the [[single cycle data break]] form of [[Direct Memory Access|DMA]] to transfer data directly to [[main memory]]. It uses blocks of 256 w
  712 bytes (111 words) - 18:25, 29 April 2021

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