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The PDP-11/24 was the last low-end UNIBUS PDP-11 system. It used the KDF11-U CPU. Like the earlier PDP-11/44, the -11/24 supported up to 4 Mbytes of main memory, using the Extended UNIBUS between the CPU and memory; all devices were attached to a semi-separate (see below) UNIBUS.

An optional UNIBUS Map board provided access to all of memory for UNIBUS DMA devices; without it, the UNIBUS address space was statically mapped across to the low 248 Kbytes of EUB main memory, using a cross-connection path on the CPU board.


The optional UNIBUS Map board, the KT24, provided a path between the UNIBUS and the EUB; the KT24 was also implemented as a single hex board, the M7134. A set of 31 mapping register pairs in the KT24 mapped 8 Kbyte blocks of UNIBUS address space to any location within the 4 Mbyte main memory address space.

If no KT24 was present, the CPU detected its absence, and turned on a set of drivers which gated the address from the UNIBUS through to the EUB. (Pin FE1 of the CPU slot, "UB to MA VIA UBMAP", is connected to a pull-up on the CPU board, and also runs to the slot where the KT24 is plugged in, where it is grounded if a KT24 is plugged in; that signal is used to generate "UB to MA", which is the cross-connection enable signal.)

System bus structure

As mentioned, the -11/24 used an EUB for the bus between the main memory and the CPU, and the UNIBUS for the bus between the CPU and devices. The two buses were not entirely separated: they shared a set of data lines, but each bus had a separate complete set of address lines.

Either the CPU, or the optional KT24, provided a path for addressing information to flow from the UNIBUS to the EUB, for DMA access to main memory by devices.

The top 256 Kbytes of the CPU's address space were devoted to the UNIBUS; the top 8 Kbytes of that were, as usual, the peripheral page.


The -11/24 used a custom 9-slot backplane (part #5413817); slot 1 was for the CPU, slot 2 could hold either EUB memory or the UNIBUS map; slots 3-6 could hold either EUB memory or UNIBUS SPC devices. Slots 7-8 were ordinary UNIBUS MUD/SPC slots, and slot 9 was an ordinary UNIBUS SPC/UNIBUS Out slot.

The EUB and UNIBUS address lines were kept totally separate in all the slots which supported the EUB (1-6); the 22-bit EUB address bus is carried on the EUB address lines (on connectors A-B), and the 18-bit UNIBUS addresses are carried on the SPC address pins (on connector E). (The lower address lines cannot be shared between the two busses, since the UNIBUS map provides arbitrary mapping from UNIBUS addresses to main memory addresses; so there are no lines which are guaranteed to have the same values, to allow them to be shared between the two busses.)

The data lines were cross-connected between the EUB and SPC/UNIBUS. That is because the DEC EUB memory boards pick up the data lines on connector A, whereas UNIBUS SPC devices must get them on connector C - and the memory/SPC slots of the -11/24 backplane can hold either.

In fact, the CPU board connects to the data bus on the C connector, i.e. the UNIBUS SPC pins. The KT24, contrastingly, uses connector A (the MUD pins) for access to the data bus. The reason for the difference is not known - perhaps board layout issues?

With no KT24, a standard EUB memory can go in slot 2; that slot is special, though (i.e. wired differently from slots 3-6). The KT24 needs not only the UNIBUS lines and EUB address lines (to map from one to the other), it also has some special interconnects with the CPU, (e.g. the 'UNIBUS adapter present' line). Bus grant lines also bypass slot 2; hence the limitation to the KT24 or memory.


The -11/24 came in two different cabinets, the 5-1/4 inch high BA11-L and the 10-1/2 inch BA11-A (the same mounting box as used in the -11/44; the backplane of the latter uses unique flat cable power connectors, though, not the standard DEC power distribution connectors used by the -11/24 backplane in the BA11-L mounting box, so it's not clear how it connects).

Memory configuration limits

The "PDP-11 UNIBUS Processor Handbook" (1985) says (pg. 4-10) that in the 5.25" box, "only one MS11-P memory module can be configured". The cause/source of that restriction is not given.

It can't be the backplane; i) the 5.25" and 10.5" (for which no limitation is stated) boxes use the same backplane, and ii) the 5.25" box can take more of the smaller MS11-L cards (albeit, again, limited - to three). The backplane does carry all 22 address lines to all EUB slots, and the CPU does drive all 22.

It's possible that it's a power supply current issue. The MS11-P only uses +5V, but there's nothing about limiting the number of other (ordinary) boards when an MS11-P is in use. The power supply specs show the BA11-L provides 32A of +5V and 4A of +5VBB; alas, the power consumption specs for the CPU and UNIBUS Map (which is basically necessary, for use of more than 256 Kbytes of memory) boards are not given.

The MS11-P uses up to 5A of +5V, and 3A of +5VBB; the MS11-L uses up to 2A of +5V, and 1.3A of +5VBB. The limited amount of +5VBB in the BA11-L does correspond to the limitations on the number of MS11-L and MS11-P boards.