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  • [[Category: PDP-11 UNIBUS Processors]]
    6 KB (1,045 words) - 22:47, 31 March 2022
  • In addition to several standard [[UNIBUS]] signals (SACK, INIT, DCLO and ACLO), it also used a pair of additional ba [[Category: PDP-11 UNIBUS Processors]]
    2 KB (358 words) - 18:29, 3 April 2022
  • ...t|VAXBI]] [[bus]]; it uses the [[KA820 CPU]]. It can support an optional [[UNIBUS]] adapter. ...-20 of the PDF) and covered in detail in Chapter 5, "VAX 8200 and VAX 8300 Processors" (pp. 86-102 of the PDF)
    2 KB (317 words) - 04:02, 19 May 2024
  • ...ect|VAXBI]] [[bus]], using the [[KA820 CPU]]; it can support an optional [[UNIBUS]] adapter. ...-20 of the PDF) and covered in detail in Chapter 5, "VAX 8200 and VAX 8300 Processors" (pp. 86-102 of the PDF)
    2 KB (287 words) - 14:43, 19 May 2024
  • The '''KS10''' was the fourth and last generation of [[PDP-10]] processors (themselves, exact re-implementations of the earlier [[PDP-6]] architecture ...Processing Unit|CPU]], the [[main memory]] controller, and two or three [[UNIBUS]] adapters (which are used to perform all [[input/output|I/O]] in the syste
    8 KB (1,237 words) - 19:48, 14 July 2023
  • [[Category: PDP-11 UNIBUS Processors]]
    4 KB (734 words) - 02:17, 13 October 2022
  • ...ing two data bytes; a tag field for cache entries, 7 bits wide (covering [[UNIBUS]] address bits 17-11); 3 [[parity]] bits (one for the tag); and two valid b [[Category: PDP-11 UNIBUS Processors]]
    4 KB (553 words) - 02:36, 12 October 2022
  • ...US [[Small Peripheral Controller|SPC]] slot; that slot also contained the 'UNIBUS out'. | 9 || colspan="2" style="text-align:center;" | UNIBUS Out || colspan="4" style="text-align:center;" | SPC
    4 KB (588 words) - 05:52, 8 April 2024
  • ...also up to two [[PDP-10 I/O Bus]]ses (allowing it to be controlled by both processors in a multi-[[Central Processing Unit|CPU]] system). So, it could be connect ...DL10, which allows the PDP-10 to start and stop the PDP-11; the PDP-11's [[UNIBUS]] runs into the DL10 and is plugged into the DL10's backplane.
    5 KB (664 words) - 17:27, 7 November 2023
  • ...[graphics terminal]]s, and provide [[Chaosnet]] [[front end]]s to [[KL10]] processors. * [[UNIBUS Experimental Ethernet interface|3 Mbit Ethernet]] interface
    3 KB (347 words) - 08:50, 27 February 2024
  • ...as a bus arbitrator, so that the machine can be a 'slave' processor, on a UNIBUS controlled by another CPU. [[Category: PDP-11 UNIBUS Processors]]
    11 KB (1,726 words) - 21:07, 2 July 2023
  • In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use the special high-speed [[MS11 Semiconductor Me * M8104 Processor Data and UNIBUS Registers
    3 KB (395 words) - 21:08, 2 July 2023
  • In addition to [[main memory]] on the [[UNIBUS]], the KB11-A could also use the special high-speed [[MS11 Semiconductor Me * M8104 Processor Data and UNIBUS Registers
    2 KB (307 words) - 12:32, 11 October 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    2 KB (231 words) - 02:38, 12 October 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    2 KB (304 words) - 02:33, 12 October 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    961 bytes (149 words) - 02:20, 13 October 2022
  • ...t|chips]], and not a [[microprocessor]], and also nearly the last native [[UNIBUS]] CPU (except for the [[KDF11-U CPU|KDF11-U]]). ...ess to the memory via a [[UNIBUS map]] which connected the two, and mapped UNIBUS addresses to main memory addresses.
    4 KB (668 words) - 15:59, 6 February 2024
  • ...o the memory via a [[UNIBUS map]] which connected the two, and also mapped UNIBUS addresses to main memory addresses. High-speed devices could be attached to * M8134 Processor Data and UNIBUS Registers
    3 KB (456 words) - 21:08, 2 July 2023
  • [[Category: PDP-11 UNIBUS Processors]]
    2 KB (260 words) - 21:03, 24 October 2022
  • ...ipheral|devices]] such as the [[RP11 disk controller]]). It carries all 56 UNIBUS [[signal]]s, and 64 [[ground]] lines (alternating with the signals, to prev ...t board|PCB]] ([[M919]] and [[M929]]), which plug into the 'UNIBUS in' or 'UNIBUS out' slot of the element's [[backplane]].
    1 KB (176 words) - 12:47, 16 October 2021
  • ...[[Central Processing Unit|CPU]] board. It can be plugged into either a [[UNIBUS]] or [[QBUS]] backpane, since it does not use the [[bus]]; it only gets pow [[Category: PDP-11 Processors]]
    2 KB (383 words) - 02:31, 12 October 2022
  • | controller = [[RC11 disk controller|RC11]] ([[UNIBUS]]) ...[[PDP-11]]s. (No [[PDP-8 family|PDP-8]] or other [[List of Programmed Data Processors|early DEC system]] [[device controller]] has yet been seen for it, although
    2 KB (258 words) - 22:12, 14 August 2023
  • It plugs into a modified [[Modified UNIBUS Device|MUD]] [[backplane]], either the the [[DD11-C backplane|DD11-C]] or [ ...bove) of the M7263. (The main functionality of the KY11-B is done over the UNIBUS, and a pair of backplane lines.)
    2 KB (385 words) - 22:37, 31 March 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    2 KB (258 words) - 00:29, 30 December 2023
  • ...[[PDP-11 Memory Management|subset PDP-11 memory management]], and used a [[UNIBUS]] for its [[main memory]] access (although a built-in [[cache]] was standar ...e memory UNIBUS; but it also indicates (pg. 3) that there is only a single UNIBUS. (Perhaps all the [[bus grant line]]s from the bus arbitration circuitry in
    4 KB (536 words) - 12:34, 11 October 2022
  • [[Category: PDP-11 UNIBUS Processors]]
    1 KB (229 words) - 02:19, 13 October 2022
  • '''On Bus Arbitration on the Unibus and QBUS''' ...ry from years ago of being told about how there was a design flaw in the [[UNIBUS]] that could, on rare occasion, lead to a bus-arbitration failure, and that
    21 KB (3,685 words) - 04:35, 28 November 2023
  • [[Category: PDP-11 UNIBUS Processors]]
    995 bytes (154 words) - 02:35, 12 October 2022
  • ...ytes; also a tag field for cache entries, 9 bits wide (covering [[Extended UNIBUS]] address bits 21-13); 3 [[parity]] bits (one for the tag); and two valid b ...IBUS]] was cached, not any memory which might be present on the ordinary [[UNIBUS]] (normally used only for [[input/output|I/O]]).
    3 KB (501 words) - 16:27, 6 February 2024
  • ...console to request that the CPU [[halt]]; this is done with the standard [[UNIBUS]] [[signal]], SACK, and a pair of additional signals, Halt Request and Gran ...[[grant continuity card]]), the machine will irretrievably 'freeze'; see [[UNIBUS and QBUS termination#SACK turnaround and CPU hangs|SACK turnaround and CPU
    4 KB (650 words) - 16:50, 4 December 2022
  • ...croprogrammable_Processors_May75.pdf A Comparison of Two Microprogrammable Processors] [[Category: UNIBUS PDP-11s]]
    1 KB (183 words) - 16:20, 11 January 2024
  • ...SACK Timeout Module''' is rare, little-known, poorly-documented optional [[UNIBUS]] board for the [[KD11-D CPU]] of the [[PDP-11/04]] and the [[KD11-E CPU]] It provides the [[UNIBUS and QBUS termination#SACK turnaround|grant timeout circuit]] which is not i
    4 KB (740 words) - 16:41, 20 April 2022
  • * L0004 [[UNIBUS]] Interface (UBI) - UNIBUS control and function, ancillary functions [[Category: DEC VAX Processors]]
    3 KB (519 words) - 03:33, 18 May 2024
  • ...the peripherals and I/O adapters. One of the latter was produced for the [[UNIBUS]]; peripherals included [[Ethernet]] and [[Computer Interconnect|CI]] inter
    3 KB (438 words) - 01:46, 8 May 2024
  • 5.7 DW780 - Unibus Adapter 11782 processors.
    70 KB (7,782 words) - 14:04, 2 July 2022
  • The '''KS11 Memory Protection and Relocation option''' was a [[UNIBUS]] option which was apparently [[Digital Equipment Corporation|DEC]]'s first ...and the [[main memory]] and [[peripheral|devices]] on the rest of the the UNIBUS (in the same manner as the [[KT11-B Paging Option]]).
    5 KB (754 words) - 17:58, 29 February 2024
  • rh11 pdp11 unibus RM02, RP04/5/6, ML11, RS03/4 rk611 pdp11 unibus RK06/7
    33 KB (4,919 words) - 12:31, 21 June 2023
  • ...s and Services for new processors while Software Products and Services for processors already introduced remained in the old 7-Character Format. *J - [[PDP-11]] [[UNIBUS]]-based ([[RT-11]], [[ULTRIX-11]])
    6 KB (972 words) - 17:56, 25 April 2024
  • [[Category: PDP-11 UNIBUS Processors]]
    831 bytes (119 words) - 21:09, 5 July 2023
  • * Only one [[interrupt]] priority level on the [[UNIBUS]] [[Category: PDP-11 UNIBUS Processors]]
    1 KB (202 words) - 01:40, 6 July 2023
  • ...ode]] in the CPU; on high-end systems, the channels were discrete physical processors. * [[DX11-B System 360/370 Channel to PDP-11 Unibus Interface]]
    5 KB (704 words) - 17:20, 9 April 2024

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