PDP-11 Memory Management
PDP-11s which provide memory management use a standard PDP-11 Memory Management architecture. When memory management is enabled, the basic 64 Kbyte address space of the PDP-11 architecture is divided into 8 'segments' (the terminology used in the first version of the documentation; it was later changed to 'pages', for unknown reasons, but this is incorrrect - the functionality provided is that of segmentation, not paging).
Each segment of a virtual address space can be individually assigned to any location in physical main memory. Each segment can be set to any length between 0 bytes and 8 Kbytes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; the latter to accomodate PDP-11 stacks, which typically grow down (from higher addresses to lower).
The CPU can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate mappings, to provide separate virtual address spaces for each mode.
An additional enhancement is that instruction and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called Split I+D space capability; this increases the memory available to the operating system, and each user, to 128 Kbytes. Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.) When split I+D is not enabled in any particular mode, only a single 64 Kbyte address space is provided, using only the I-space registers for that mode.
If any instruction causes a fault (i.e. an attempt to perform a memory operation which cannot be completed, because of the settings of the memory management - e.g. an attempt to write into a segment set as 'read only'), execution of the instruction is aborted, and a memory management trap occurs.
A number of the smaller PDP-11's (notably the PDP-11/40, PDP-11/34, PDP-11/60, PDP-11/23 and PDP-11/24) provide only a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).
Also, there is no SSR1 register (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out' to their state before the instruction started execution), and in some cases impossible (e.g. instructions which auto-increment the same register several times).
The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which keep most of the information needed for memory management in page tables held in main memory, and cached in the CPU).
There are four registers which control the overall operation of the Memory Management Unit:
|777572||SSR0||Control and status|
|777574||SSR1||Register increment/decrement record|
|777576||SSR2||Virtual address associated with the fault (usually the instruction address)|
|777516||SSR3||D-space enable/disable (per mode)|
The names were changed to SR0-SR3 after the 'Segmentation' term was dropped from the name; the forms MMR0-MMR3 are also occasionally met with. On the 'simplified subset' machines, SSR1 and (usually) SSR3 are not implemented (the KDF11 CPUs are an exception to the latter; see below).
SSR0 contains control bits (e.g. enabling memory management) and status bits (e.g. information about memory operations which caused a memory management fault, and the segment involved). The layout of SSR0 is:
|Non-resident||Length||Read-only||Trap||Unused||Enable Trap||Maintenance||Instruction Completed||CPU Mode||I/D||Page||Enable|
When any of the first three bits (all error aborts) are set, bits 1-7, as well as SSR1 and SSR2, are frozen. On the 'simplified subset' machines, bits 12, 9, 7 and 4 are not implemented.
SSR1 contains information about register modifications (given there in two's complement) performed during the course of an instruction, to allow those modifications to be 'backed out' if the instruction needs to be restarted after a memory management fault. Its layout is:
SSR2 contains the address of the instruction which caused the memory management fault.
SSR3 contains bits to enable Split I+D in the three modes; on machines which have UNIBUS maps, the enable for it is also here. Its layout is:
|Unused||Enable UNIBUS Map||Enable 22-bit||Unused||Kernel||Supervisor||User|
PARs and PDRs
Each segment (up to 48 in total; 8 each Instruction and Data, for the three different modes) is described by a pair of registers, a Page Descriptor Register (PDR) and a Page Address Register (PAR).
The PAR contains the base physical address for the segment (in units of 0100/64. bytes). On machines which have only UNIBUS memory (e.g. PDP-11/40, PDP-11/45, etc) these registers are 12 bits long, since the maximum amount of physical memory on these machines is 248 Kbytes. On machines which support up to 4 MBytes of physical memory (e.g. PDP-11/70, PDP-11/44, PDP-11/23, etc), they are 16 bits long.
The PDR contains the segment's length, along with the direction of growth, the access control field (read/only, read/write, etc), a 'dirty' bit (maintained by the hardware), etc. The layout of the PDR is:
|Don't Cache||Length||Trapped||Written||Unused||Direction||Access Control|
The values of the 'Access Control' field are:
|0||Non-resident - abort all accesses|
|1||Read-only watched - abort on write, trap on read|
|2||Read-only - abort on write|
|3||Unused, reserved - abort all accesses|
|4||Read/write all watched - trap on read or write|
|5||Read/write watched - trap on write|
|6||Read/write - none|
|7||Unused, reserved - abort all accesses|
On the 'simplified subset' machines, only modes 0, 2 and 6 are supported, and neither is the 'Trapped' bit (set on PDR's for memory references that trapped, on the other machines).
The 'Don't Cache' bit is only available on the KDJ11 CPUs.
The addresses of the PAR/PDR sets are:
|772200||SISD0||Supervisor I-Space PDR #0|
|772216||SISD7||Supervisor I-Space PDR #7|
|772220||SDSD0||Supervisor D-Space PDR #0|
|772236||SDSD7||Supervisor D-Space PDR #7|
|772240||SISA0||Supervisor I-Space PAR #0|
|772256||SISA7||Supervisor I-Space PAR #7|
|772260||SDSA0||Supervisor D-Space PAR #0|
|772276||SDSA7||Supervisor D-Space PAR #7|
|772300||KISD0||Kernel I-Space PDR #0|
|772316||KISD7||Kernel I-Space PDR #7|
|772320||KDSD0||Kernel D-Space PDR #0|
|772336||KDSD7||Kernel D-Space PDR #7|
|772340||KISA0||Kernel I-Space PAR #0|
|772356||KISA7||Kernel I-Space PAR #7|
|772360||KDSA0||Kernel D-Space PAR #0|
|772376||KDSA7||Kernel D-Space PAR #7|
|777600||UISD0||User I-Space PDR #0|
|777616||UISD7||User I-Space PDR #7|
|777620||UDSD0||User D-Space PDR #0|
|777636||UDSD7||User D-Space PDR #7|
|777640||UISA0||User I-Space PAR #0|
|777656||UISA7||User I-Space PAR #7|
|777660||UDSA0||User D-Space PAR #0|
|777676||UDSA7||User D-Space PAR #7|
- A Segmentation Scheme for the PDP-11 Family - interesting design memo