PDP-11 Memory Management

From Computer History Wiki
Jump to: navigation, search

PDP-11s which provide memory management use a standard PDP-11 Memory Management architecture. When memory management is enabled, the basic 64 Kbyte address space of the PDP-11 architecture is divided into 8 segments; each segment of the virtual address space can be assigned to any location in physical memory.

Each segment can be set to any length between 0 bytes and 8 Kbtes, in 0100 (64.) byte increments. Segments can grow either up from their base address, or down; this is to accomodate PDP-11 stacks, which typically grow down (from higher addresses to lower).

The machine can be in one of three modes; 'Kernel', 'Supervisor', and 'User'; each has its own separate set of mapping registers, to provide separate virtual address spaces for each mode.

An additional enhancement is that instruction and data fetches can be set to go to separate 64 Kbyte address spaces, the so-called Split I+D space capability; this increases the memory available to the operating system, and each user, to 128 Kbytes.

(Since immediate operands and absolute addresses are stored contiguous with their instructions, fetches of them are considered to be instruction fetches, for the purposes of deciding which space to use for them.)

If any instruction causes a fault (i.e. an attempt to perform a memory operation which cannot be completed, because of the settings of the memory management - e.g. an attempt to write into a segment set as 'read only'), execution of the instruction is aborted, and a memory managemen trap occurs.

Simplified subset

A number of the smaller PDP-11's (notably the PDP-11/40, PDP-11/34 and PDP-11/23) only provide a limited subset of the standard memory management facilities. In these machines, there is no support for Split I+D, and no Supervisor mode (just Kernel and User).

Also, there is no SSR1 register (below), which can make re-starting instructions which cause a fault laborious (the fault-handling code has to decipher the instruction and effectively simulate its operation, to work out which registers need to be 'backed out'), and in some cases impossible (e.g. instructions which auto-increment the same register several times).


The memory management is entirely controlled by groups of registers in the CPU (unlike many virtual memory systems, which use page tables held in main memory, and cached in the CPU).


There are four registers which control the overall operation of the Memory Management Unit:

Address Name Function
777572 SSR0 Control and status
777574 SSR1 Register increment/descrement record
777576 SSR2 Virtual address associated with the fault (usually the instruction address)
777516 SSR3 D-space enable/disable (per mode)

SSR0 contains control bits (e.g. enabling memory management) and status bits (e.g. information about memory operations which caused a memory management fault, and the segment involved).

SSR1 contains information about register modifications performed during the course of an instruction, to allow those modifications to be 'backed out' if the instruction needs to be restarted after a memory management fault.

SSR2 contains the address of the instruction which caused the memory management fault.

SSR3 contains bits to enable Split I+D in the three modes; on machines which have UNIBUS maps, the enable for it is also here.

PARs and PDRs

Each segment (up to 48 in total; 8 each Instruction and Data, for the three different modes) is described by a pair of registers, a Page Descriptor Register (PDR) and a Page Address Register (PAR).

The PAR contains the base physical address for the segment (in units of 0100/64. bytes). On machines which have only UNIBUS memory (e.g. PDP-11/40, PDP-11/45, etc) these registers are 12 bits long, since the maximum amount of physical memory on these machines is 248 Kbytes. On machines which support up to 4 MBytes of physical memory (e.g. PDP-11/70, PDP-11/44, PDP-11/23, etc), they are 16 bits long.

The PDR contains the segment's length, along with the direction of growth, the access control field (read/only, read/write, etc), a 'dirty' bit (maintained by the hardware), etc.

When split I+D is not enabled in any particular mode, only a single 64 Kbyte address space is provided, using only the I-space registers for that mode.

The addresses of the PAR/PDR sets are:

Address Name Function
772200 SISD0 Supervisor I-Space PDR #0
772216 SISD7 Supervisor I-Space PDR #7
772220 SDSD0 Supervisor D-Space PDR #0
772236 SDSD7 Supervisor D-Space PDR #7
772240 SISA0 Supervisor I-Space PAR #0
772256 SISA7 Supervisor I-Space PAR #7
772260 SDSA0 Supervisor D-Space PAR #0
772276 SDSA7 Supervisor D-Space PAR #7
772300 KISD0 Kernel I-Space PDR #0
772316 KISD7 Kernel I-Space PDR #7
772320 KDSD0 Kernel D-Space PDR #0
772336 KDSD7 Kernel D-Space PDR #7
772340 KISA0 Kernel I-Space PAR #0
772356 KISA7 Kernel I-Space PAR #7
772360 KDSA0 Kernel D-Space PAR #0
772376 KDSA7 Kernel D-Space PAR #7
777600 UISD0 User I-Space PDR #0
777616 UISD7 User I-Space PDR #7
777620 UDSD0 User D-Space PDR #0
777636 UDSD7 User D-Space PDR #7
777640 UISA0 User I-Space PAR #0
777656 UISA7 User I-Space PAR #7
777660 UDSA0 User D-Space PAR #0
777676 UDSA7 User D-Space PAR #7